mirror of
https://github.com/EttusResearch/uhd.git
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110 lines
2.7 KiB
Verilog
110 lines
2.7 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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task SendFlowCtrl;
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input [15:0] fc_len;
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begin
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$display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
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//pause_time <= fc_len;
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@(posedge eth_clk);
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//pause_req <= 1;
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@(posedge eth_clk);
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//pause_req <= 0;
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$display("Sent Flow Control");
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end
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endtask // SendFlowCtrl
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task SendPacket_to_fifo36;
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input [31:0] data_start;
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input [15:0] data_len;
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reg [15:0] count;
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begin
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$display("Sending Packet Len=%d, %d", data_len, $time);
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count <= 2;
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tx_f36_data <= {2'b0, 1'b0, 1'b1, data_start};
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tx_f36_src_rdy <= 1;
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#1;
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while(count < data_len)
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begin
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while(~tx_f36_dst_rdy)
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@(posedge sys_clk);
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@(posedge sys_clk);
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tx_f36_data[31:0] = tx_f36_data[31:0] + 32'h0101_0101;
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count = count + 4;
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tx_f36_data[32] <= 0;
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end
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tx_f36_data[33] <= 1;
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while(~tx_f36_dst_rdy)
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@(posedge sys_clk);
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@(posedge sys_clk);
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tx_f36_src_rdy <= 0;
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end
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endtask // SendPacket_to_fifo36
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/*
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task Waiter;
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input [31:0] wait_length;
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begin
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tx_ll_src_rdy2 <= 0;
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repeat(wait_length)
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@(posedge clk);
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tx_ll_src_rdy2 <= 1;
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end
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endtask // Waiter
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*/
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/*
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task SendPacketFromFile_f36;
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input [31:0] data_len;
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input [31:0] wait_length;
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input [31:0] wait_time;
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integer count;
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begin
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$display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time);
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$readmemh("test_packet.mem",pkt_rom );
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while(~tx_f36_dst_rdy)
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@(posedge clk);
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tx_f36_data <= pkt_rom[0];
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tx_f36_src_rdy <= 1;
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tx_f36_eof <= 0;
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@(posedge clk);
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for(i=1;i<data_len-1;i=i+1)
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begin
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while(~tx_ll_dst_rdy2)
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@(posedge clk);
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tx_ll_data2 <= pkt_rom[i];
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tx_ll_sof2 <= 0;
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@(posedge clk);
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// if(i==wait_time)
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// Waiter(wait_length);
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end
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while(~tx_ll_dst_rdy2)
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@(posedge clk);
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tx_ll_eof2 <= 1;
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tx_ll_data2 <= pkt_rom[data_len-1];
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@(posedge clk);
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tx_ll_src_rdy2 <= 0;
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end
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endtask
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*/
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