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58 lines
1.4 KiB
Verilog
58 lines
1.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module sd_spi_tb;
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reg clk = 0;
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always #5 clk = ~clk;
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reg rst = 1;
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initial #32 rst = 0;
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wire sd_clk, sd_mosi, sd_miso;
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wire [7:0] clk_div = 12;
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wire [7:0] send_dat = 23;
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wire [7:0] rcv_dat;
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wire ready;
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reg go = 0;
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initial
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begin
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repeat (100)
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@(posedge clk);
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go <= 1;
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@(posedge clk);
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go <= 0;
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end
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sd_spi dut(.clk(clk),.rst(rst),
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.sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
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.clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat),
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.go(go),.ready(ready) );
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initial
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begin
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$dumpfile("sd_spi_tb.vcd");
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$dumpvars(0,sd_spi_tb);
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end
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initial
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#10000 $finish();
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endmodule // sd_spi_tb
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