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88 lines
3.1 KiB
Systemverilog
88 lines
3.1 KiB
Systemverilog
//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: synchronizer_sync_in
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//
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// Description:
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//
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// This is a synchronizer module designed for a synchronous input. This
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// synchronizer should be used any time you want to cross a synchronous
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// signal that is not driven by a flip-flop to another clock domain.
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//
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// Combinational logic outputs require a flip-flop to filter any glitches
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// before being crossed to another clock domain. This module consists of a
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// standard "synchronizer" module with an input flip-flop on the driving
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// clock domain to filter these glitches. A block diagram of this module is
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// shown below.
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//
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// Input Flip-Flop Synchronizer
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//
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// i_sig ┌───┐ ┌───┐ ┌───┐ o_sig
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// ─────────►│ ├───────────────►│ ├───►│ ├─────►
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// ┌─►│ │ ┌───►│ │ ┌─►│ │
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// │ └───┘ │ └───┘ │ └───┘
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// │ │ │
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// i_clk │ │ │
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// ───────┘ │ │
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// │ │
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// o_clk │ │
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// ──────────────────────────┴──────────┘
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//
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// Parameters:
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//
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// WIDTH : Width of the synchronizer (1 by default). Note that this
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// module does not ensure coherence between bits. Multi-bit
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// signals should normally use the handshake module instead of
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// this module to ensure that all output bits arrive at the
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// same time.
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// STAGES : Number of synchronizer stages (3 by default, for a
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// triple-synchronizer).
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// INITIAL_VAL : Initial and reset value of the registers (0 by default).
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//
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`default_nettype none
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module synchronizer_sync_in #(
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int WIDTH = 1,
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int STAGES = 3,
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logic INITIAL_VAL = 0
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) (
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input wire i_clk,
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input wire i_rst,
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input wire [WIDTH-1:0] i_sig,
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input wire o_clk,
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input wire o_rst,
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output wire [WIDTH-1:0] o_sig
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);
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logic [WIDTH-1:0] i_sig_reg = { WIDTH {INITIAL_VAL}};
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// Filter any glitches from combinational logic by registering the input
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always_ff @(posedge i_clk) begin
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if (i_rst) begin
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i_sig_reg <= { WIDTH {INITIAL_VAL}};
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end else begin
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i_sig_reg <= i_sig;
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end
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end
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synchronizer #(
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.WIDTH (WIDTH ),
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.STAGES (STAGES ),
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.INITIAL_VAL (INITIAL_VAL),
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.FALSE_PATH_TO_IN(1 )
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) synchronizer_i (
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.clk(o_clk ),
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.rst(o_rst ),
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.in (i_sig_reg),
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.out(o_sig )
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);
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endmodule : synchronizer_sync_in
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`default_nettype wire
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