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168 lines
6.9 KiB
Verilog
168 lines
6.9 KiB
Verilog
//
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// Copyright 2011-2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//////////////////////////////////////////////////////////////////////////////////
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module gpmc
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#(parameter TXFIFOSIZE = 11,
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parameter RXFIFOSIZE = 11,
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parameter ADDR_WIDTH = 10,
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parameter BUSDEBUG = 1)
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(// GPMC signals
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input arst,
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input EM_CLK, inout [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input [1:0] EM_NBE,
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input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
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// GPIOs for FIFO signalling
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output rx_have_data, output tx_have_space, output resp_have_data,
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// FIFO interface
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input fifo_clk, input fifo_rst,
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output [35:0] tx_data, output tx_src_rdy, input tx_dst_rdy,
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input [35:0] rx_data, input rx_src_rdy, output rx_dst_rdy,
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output [35:0] ctrl_data, output ctrl_src_rdy, input ctrl_dst_rdy,
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input [35:0] resp_data, input resp_src_rdy, output resp_dst_rdy,
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output [31:0] debug
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);
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wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
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wire [15:0] EM_D_data;
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wire [15:0] EM_D_ctrl;
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assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_data : EM_D_ctrl;
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// CS4 is RAM_2PORT for DATA PATH (high-speed data)
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// Writes go into one RAM, reads come from the other
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// CS6 is for CONTROL PATH (slow)
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// ////////////////////////////////////////////
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// TX Data Path
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wire [17:0] tx18_data;
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wire tx18_src_rdy, tx18_dst_rdy;
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wire [35:0] txb_data;
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wire txb_src_rdy, txb_dst_rdy;
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gpmc_to_fifo #(.ADDR_WIDTH(10), .LAST_ADDR(10'h3ff), .PTR_WIDTH(2)) gpmc_to_fifo
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(.EM_D(EM_D), .EM_A(EM_A[10:1]), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS4 & ~EM_NWE),
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.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
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.data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
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.have_space(tx_have_space));
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fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE
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(.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
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.f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy),
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.f36_dataout(txb_data), .f36_src_rdy_o(txb_src_rdy), .f36_dst_rdy_i(txb_dst_rdy));
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fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_buffering(
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.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
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.datain(txb_data), .src_rdy_i(txb_src_rdy), .dst_rdy_o(txb_dst_rdy),
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.dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy)
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);
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// ////////////////////////////////////////////
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// RX Data Path
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wire [17:0] rx18_data;
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wire rx18_src_rdy, rx18_dst_rdy;
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wire [35:0] rxb_data;
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wire rxb_src_rdy, rxb_dst_rdy;
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wire dummy;
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fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_buffering(
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.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
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.datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy),
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.dataout(rxb_data), .src_rdy_o(rxb_src_rdy), .dst_rdy_i(rxb_dst_rdy)
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);
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fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE
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(.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
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.f36_datain(rxb_data), .f36_src_rdy_i(rxb_src_rdy), .f36_dst_rdy_o(rxb_dst_rdy),
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.f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
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fifo_to_gpmc #(.ADDR_WIDTH(ADDR_WIDTH), .LAST_ADDR(10'h3ff)) fifo_to_gpmc
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(.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
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.data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy),
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.EM_D(EM_D_data), .EM_A(EM_A), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS4 & ~EM_NOE),
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.data_available(rx_have_data));
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// ////////////////////////////////////////////
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// Control path on CS6
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// ////////////////////////////////////////////////////////////////////
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// CTRL TX Data Path
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wire [17:0] ctrl18_data;
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wire ctrl18_src_rdy, ctrl18_dst_rdy;
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wire [35:0] ctrlb_data;
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wire ctrlb_src_rdy, ctrlb_dst_rdy;
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gpmc_to_fifo #(.PTR_WIDTH(5), .ADDR_WIDTH(5), .LAST_ADDR(5'h0f)) ctrl_gpmc_to_fifo
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(.EM_D(EM_D), .EM_A(EM_A[5:1]), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS6 & ~EM_NWE),
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.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
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.data_o(ctrl18_data), .src_rdy_o(ctrl18_src_rdy), .dst_rdy_i(ctrl18_dst_rdy),
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.have_space(/*always*/));
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fifo19_to_fifo36 #(.LE(1)) ctrl_f19_to_f36 // Little endian because ARM is LE
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(.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
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.f19_datain({1'b0,ctrl18_data}), .f19_src_rdy_i(ctrl18_src_rdy), .f19_dst_rdy_o(ctrl18_dst_rdy),
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.f36_dataout(ctrlb_data), .f36_src_rdy_o(ctrlb_src_rdy), .f36_dst_rdy_i(ctrlb_dst_rdy));
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fifo_cascade #(.WIDTH(36), .SIZE(9)) ctrl_buffering(
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.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
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.datain(ctrlb_data), .src_rdy_i(ctrlb_src_rdy), .dst_rdy_o(ctrlb_dst_rdy),
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.dataout(ctrl_data), .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy)
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);
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// ////////////////////////////////////////////
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// CTRL RX Data Path
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wire [17:0] resp18_data;
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wire resp18_src_rdy, resp18_dst_rdy;
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wire [35:0] respb_data;
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wire respb_src_rdy, respb_dst_rdy;
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wire resp_dummy;
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fifo_cascade #(.WIDTH(36), .SIZE(9)) resp_buffering(
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.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
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.datain(resp_data), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy),
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.dataout(respb_data), .src_rdy_o(respb_src_rdy), .dst_rdy_i(respb_dst_rdy)
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);
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fifo36_to_fifo19 #(.LE(1)) resp_f36_to_f19 // Little endian because ARM is LE
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(.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
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.f36_datain(respb_data), .f36_src_rdy_i(respb_src_rdy), .f36_dst_rdy_o(respb_dst_rdy),
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.f19_dataout({resp_dummy,resp18_data}), .f19_src_rdy_o(resp18_src_rdy), .f19_dst_rdy_i(resp18_dst_rdy) );
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fifo_to_gpmc #(.PTR_WIDTH(5), .ADDR_WIDTH(5), .LAST_ADDR(5'h0f)) resp_fifo_to_gpmc
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(.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
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.data_i(resp18_data), .src_rdy_i(resp18_src_rdy), .dst_rdy_o(resp18_dst_rdy),
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.EM_D(EM_D_ctrl), .EM_A(EM_A[5:1]), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS6 & ~EM_NOE),
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.data_available(resp_have_data));
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//*
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assign debug = {
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EM_D,
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//resp18_data[15:0], //16
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EM_A, //10
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//resp18_data[17:16], resp18_src_rdy, resp18_dst_rdy, //4
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EM_NCS4, EM_NCS6, EM_NWE, EM_NOE, //4
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EM_CLK, resp_have_data //2
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};
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//*/
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endmodule // gpmc
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