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Update the X4xx SPI core, radio-control integration, examples, and tests for transactions up to 64 bits and the revised register map.
159 lines
6.3 KiB
C++
159 lines
6.3 KiB
C++
//
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// Copyright 2026 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: GPL-3.0-or-later
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//
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// Example for SPI testing.
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//
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// This example shows how to work with SPI which is based on the GPIO
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// interface of the X410.
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#include <uhd/features/spi_getter_iface.hpp>
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#include <uhd/usrp/multi_usrp.hpp>
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#include <uhd/utils/safe_main.hpp>
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#include <stdlib.h>
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#include <boost/program_options.hpp>
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#include <cstdint>
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#include <iostream>
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static const size_t SPI_DEFAULT_CLK_PIN = 0;
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static const size_t SPI_DEFAULT_SDI_PIN = 1;
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static const size_t SPI_DEFAULT_SDO_PIN = 2;
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static const size_t SPI_DEFAULT_CS_PIN = 3;
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static const size_t SPI_DEFAULT_PAYLOAD_LENGTH = 32;
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static const std::string SPI_DEFAULT_PAYLOAD = "0xfefe";
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namespace po = boost::program_options;
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int UHD_SAFE_MAIN(int argc, char* argv[])
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{
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// variables to be set by po
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std::string args;
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size_t clk;
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size_t sdi;
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size_t sdo;
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size_t cs;
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size_t payload_length;
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size_t clk_divider;
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std::string payload_str;
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uint64_t payload;
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// setup the program options
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po::options_description desc("Allowed options");
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// clang-format off
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desc.add_options()
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("help", "help message")
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("args", po::value<std::string>(&args)->default_value(""), "multi uhd device address args")
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("list-banks", "print list of banks before running tests")
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("clk", po::value<size_t>(&clk)->default_value(SPI_DEFAULT_CLK_PIN), "number of pin for SPI clock")
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("sdo", po::value<size_t>(&sdo)->default_value(SPI_DEFAULT_SDO_PIN), "number of pin for serial data out")
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("sdi", po::value<size_t>(&sdi)->default_value(SPI_DEFAULT_SDI_PIN), "number of pin for serial data in")
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("cs", po::value<size_t>(&cs)->default_value(SPI_DEFAULT_CS_PIN), "number of pin for chip select")
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("payload", po::value<std::string>(&payload_str)->default_value(SPI_DEFAULT_PAYLOAD), "payload as integer value")
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("length", po::value<size_t>(&payload_length)->default_value(SPI_DEFAULT_PAYLOAD_LENGTH), "payload length in bits")
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("clk-div", po::value<size_t>(&clk_divider), "clock divider for SPI")
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;
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// clang-format on
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po::variables_map vm;
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po::store(po::parse_command_line(argc, argv, desc), vm);
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po::notify(vm);
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// print the help message
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if (vm.count("help")) {
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std::cout << argv[0] << " " << desc << std::endl;
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return ~0;
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}
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// create a usrp device
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std::cout << std::endl;
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std::cout << "Creating the usrp device with: " << args << "..." << std::endl;
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auto usrp = uhd::usrp::multi_usrp::make(args);
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if (vm.count("list-banks")) {
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std::cout << "Available GPIO banks: " << std::endl;
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auto banks = usrp->get_gpio_banks(0);
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for (auto& bank : banks) {
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std::cout << "* " << bank << std::endl;
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}
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}
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// Get the SPI getter interface from where we'll get the SPI interface itself
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if (!usrp->get_radio_control().has_feature<uhd::features::spi_getter_iface>()) {
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std::cout << "Error: Could not find SPI_Getter_Iface. Please check if your FPGA "
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"image is up to date.\n";
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return EXIT_FAILURE;
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}
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auto& spi_getter_iface =
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usrp->get_radio_control().get_feature<uhd::features::spi_getter_iface>();
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// Set all available pins to SPI for GPIO0 and GPIO1
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std::vector<std::string> sources(12, "DB0_SPI");
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usrp->set_gpio_src("GPIO0", sources);
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usrp->set_gpio_src("GPIO1", sources);
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// Create peripheral configuration per peripheral
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uhd::features::spi_periph_config_t periph_cfg;
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periph_cfg.periph_clk = clk;
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periph_cfg.periph_sdi = sdi;
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periph_cfg.periph_sdo = sdo;
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periph_cfg.periph_cs = cs;
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// The vector holds the peripheral configs with index=peripheral number
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std::vector<uhd::features::spi_periph_config_t> periph_cfgs;
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periph_cfgs.push_back(periph_cfg);
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// Set the data direction register
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uint32_t outputs = 0x0;
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outputs |= 1 << periph_cfg.periph_clk;
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outputs |= 1 << periph_cfg.periph_sdo;
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outputs |= 1 << periph_cfg.periph_cs;
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usrp->set_gpio_attr("GPIOA", "DDR", outputs & 0xFFFFFF);
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auto spi_ref = spi_getter_iface.get_spi_ref(periph_cfgs);
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std::cout << "Using pins: " << std::endl
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<< " Clock = " << (int)(periph_cfg.periph_clk) << std::endl
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<< " SDO = " << (int)(periph_cfg.periph_sdo) << std::endl
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<< " SDI = " << (int)(periph_cfg.periph_sdi) << std::endl
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<< " CS = " << (int)(periph_cfg.periph_cs) << std::endl
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<< std::endl;
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payload = strtoull(payload_str.c_str(), NULL, 0);
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const size_t max_payload_bits = 64;
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if (payload_length == 0 || payload_length > max_payload_bits) {
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std::cerr << "Error: --length must be between 1 and " << max_payload_bits
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<< " bits." << std::endl;
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return EXIT_FAILURE;
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}
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const uint64_t payload_mask =
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payload_length == 64 ? UINT64_MAX : (UINT64_C(1) << payload_length) - UINT64_C(1);
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if (payload & ~payload_mask) {
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std::cout << "WARNING: Payload 0x" << std::hex << payload
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<< " has bits set outside of the specified length " << std::dec
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<< payload_length << " bits. Remaining payload 0x" << std::hex
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<< (payload & payload_mask) << std::endl;
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payload &= payload_mask;
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}
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std::cout << "Writing payload: 0x" << std::hex << payload << " with length "
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<< std::dec << payload_length << " bits" << std::endl;
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// The spi_config_t holds items like the clock divider and the SDI and SDO edges
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uhd::spi_config_t config;
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if (vm.count("clk-div")) {
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config.divider = clk_divider;
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config.use_custom_divider = true;
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}
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config.mosi_edge = config.EDGE_RISE;
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config.miso_edge = config.EDGE_FALL;
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// Do the SPI transaction. There are write() and read() methods available, too.
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std::cout << "Performing SPI transaction..." << std::endl;
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const uint64_t read_data =
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payload_length > 32
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? spi_ref->transact_spi64(0, config, payload, payload_length, true)
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: spi_ref->transact_spi32(
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0, config, static_cast<uint32_t>(payload), payload_length, true);
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std::cout << "Data read: 0x" << std::hex << read_data << std::endl;
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return EXIT_SUCCESS;
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}
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