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133 lines
4.4 KiB
C++
133 lines
4.4 KiB
C++
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: GPL-3.0-or-later
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//
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#pragma once
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#include <uhd/types/memmap_iface.hpp>
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#include <uhd/types/time_spec.hpp>
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#include <cstdint>
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#include <memory>
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#include <string>
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#include <vector>
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namespace uhd { namespace rfnoc { namespace x400 {
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/*! \brief Control class for the RFDC components of a single daughterboard.
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*
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* This class controls the NCOs and other RFDC settings. The corresponding FPGA
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* module is rfdc_timing_control.sv.
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*/
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class rfdc_control
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{
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public:
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using sptr = std::shared_ptr<rfdc_control>;
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//! Default SYSREF wait time for an NCO reset, in SYSREF cycles
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static constexpr uint32_t DEFAULT_SYSREF_WAIT_CYCLES = 14;
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struct regmap
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{
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//! Address of the NCO reset register
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static constexpr uint32_t NCO_RESET = 0;
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//! Bit position of reset-start bit (w)
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static constexpr uint32_t NCO_RESET_START_MSB = 0;
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//! Bit position of reset-done bit (r)
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static constexpr uint32_t NCO_RESET_DONE_MSB = 1;
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//! Bit position of nco-sync-failed bit (r)
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static constexpr uint32_t NCO_SYNC_FAILED_MSB = 8;
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//! Bit position of sysref wait time register(w)
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static constexpr uint32_t SYSREF_WAIT_LSB = 16;
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//! Bit position of sysref-wait-write-enable bit (w)
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static constexpr uint32_t WRITE_SYSREF_WAIT = 24;
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//! Address of the gearbox reset register
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static constexpr uint32_t GEARBOX_RESET = 4;
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//! Bit position of ADC gearbox reset
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static constexpr uint32_t ADC_RESET_MSB = 0;
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//! Bit position of DAC gearbox reset
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static constexpr uint32_t DAC_RESET_MSB = 1;
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};
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//! Identify the NCOs/ADCs/DACs available to this radio control
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enum class rfdc_type { RX0, RX1, RX2, RX3, TX0, TX1, TX2, TX3 };
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rfdc_control(uhd::memmap32_iface_timed&& iface, const std::string& log_id);
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/*! \brief Reset the listed NCOs.
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*
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* All NCOs that are listed in \p ncos are reset synchronously.
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*
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* \param ncos A list of NCOs that shall be reset at the given time
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* \param time The time at which the reset shall occur
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*/
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void reset_ncos(const std::vector<rfdc_type>& ncos, const uhd::time_spec_t& time);
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/*! \brief Reset the listed gearboxes.
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*
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* All gearboxes that are listed in \p gearboxes are reset synchronously.
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*
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* \param gearboxes A list of gearboxes that shall be reset at the given time
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* \param time The time at which the reset shall occur. Note: If \p time is
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* set to ASAP, the resets will still occur synchronously, but
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* at a non-deterministic time. This will suffice for synchronizing
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* gearboxes on a single device.
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*/
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void reset_gearboxes(
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const std::vector<rfdc_type>& gearboxes, const uhd::time_spec_t& time);
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//! Return true if the NCO is out of reset
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bool get_nco_reset_done();
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//! Return true if the failure flag is NOT set and the NCO is out of reset
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bool get_nco_good();
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/*! Return true if the NCO fail flag is NOT set
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*
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* Note: The logic inversion is to stay consistent with the previous
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* get_nco_*() methods; in all three cases we return 'true' if we have a
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* positive status.
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*/
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bool get_nco_no_fail();
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/*! \brief Set an NCO to a specific frequency.
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*
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* \param nco Which NCO to re-tune
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* \param freq The new frequency to tune it to (in Hz)
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*/
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double set_nco_freq(const rfdc_type nco, const double freq);
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private:
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//! Peek/poke interface
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memmap32_iface_timed _iface;
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//! Prefix for log messages
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const std::string _log_id;
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};
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constexpr std::initializer_list<rfdc_control::rfdc_type> RX_RFDC = {
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rfdc_control::rfdc_type::RX0,
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rfdc_control::rfdc_type::RX1,
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rfdc_control::rfdc_type::RX2,
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rfdc_control::rfdc_type::RX3};
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constexpr std::initializer_list<rfdc_control::rfdc_type> TX_RFDC = {
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rfdc_control::rfdc_type::TX0,
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rfdc_control::rfdc_type::TX1,
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rfdc_control::rfdc_type::TX2,
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rfdc_control::rfdc_type::TX3};
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template <typename T, typename F>
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void indexed_for(const T& range, const size_t limit, F&& func)
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{
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std::size_t i = 0;
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for (auto it = std::begin(range); it != std::end(range); ++it) {
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if (i < limit) {
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func(*it, i++);
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} else {
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break;
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}
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}
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}
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}}} // namespace uhd::rfnoc::x400
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