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daaf1ef1e1
Several files in UHD include headers or reference namespaces from Boost without using them. We clear those out for a better view of how much Boost is left in UHD.
121 lines
3.2 KiB
C++
121 lines
3.2 KiB
C++
//
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// Copyright 2013 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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//
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// Original ADF4001 driver written by: bistromath
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// Mar 1, 2013
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//
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// Re-used and re-licensed with permission.
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//
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// SPDX-License-Identifier: GPL-3.0-or-later
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//
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#pragma once
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#include <uhd/types/serial.hpp>
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#include <uhdlib/usrp/cores/spi_core_3000.hpp>
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#include <stdint.h>
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namespace uhd { namespace usrp {
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class adf4001_regs_t
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{
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public:
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/* Function prototypes */
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uint32_t get_reg(uint8_t addr);
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adf4001_regs_t(void);
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/* Register values / addresses */
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uint16_t ref_counter; // 14 bits
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uint16_t n; // 13 bits
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uint8_t charge_pump_current_1; // 3 bits
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uint8_t charge_pump_current_2; // 3 bits
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enum anti_backlash_width_t {
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ANTI_BACKLASH_WIDTH_2_9NS = 0,
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ANTI_BACKLASH_WIDTH_1_3NS = 1,
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ANTI_BACKLASH_WIDTH_6_0NS = 2,
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ANTI_BACKLASH_WIDTH_2_9NS_WAT = 3
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};
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anti_backlash_width_t anti_backlash_width;
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enum lock_detect_precision_t {
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LOCK_DETECT_PRECISION_3CYC = 0,
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LOCK_DETECT_PRECISION_5CYC = 1
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};
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lock_detect_precision_t lock_detect_precision;
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enum charge_pump_gain_t { CHARGE_PUMP_GAIN_1 = 0, CHARGE_PUMP_GAIN_2 = 1 };
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charge_pump_gain_t charge_pump_gain;
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enum counter_reset_t { COUNTER_RESET_NORMAL = 0, COUNTER_RESET_RESET = 1 };
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counter_reset_t counter_reset;
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enum power_down_t {
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POWER_DOWN_NORMAL = 0,
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POWER_DOWN_ASYNC = 1,
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POWER_DOWN_SYNC = 3
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};
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power_down_t power_down;
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enum muxout_t {
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MUXOUT_TRISTATE_OUT = 0,
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MUXOUT_DLD = 1,
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MUXOUT_NDIV = 2,
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MUXOUT_AVDD = 3,
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MUXOUT_RDIV = 4,
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MUXOUT_NCH_OD_ALD = 5,
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MUXOUT_SDO = 6,
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MUXOUT_GND = 7
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};
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muxout_t muxout;
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enum phase_detector_polarity_t {
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PHASE_DETECTOR_POLARITY_NEGATIVE = 0,
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PHASE_DETECTOR_POLARITY_POSITIVE = 1
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};
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phase_detector_polarity_t phase_detector_polarity;
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enum charge_pump_mode_t { CHARGE_PUMP_NORMAL = 0, CHARGE_PUMP_TRISTATE = 1 };
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charge_pump_mode_t charge_pump_mode;
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enum fastlock_mode_t {
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FASTLOCK_MODE_DISABLED = 0,
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FASTLOCK_MODE_1 = 1,
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FASTLOCK_MODE_2 = 2
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};
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fastlock_mode_t fastlock_mode;
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enum timer_counter_control_t {
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TIMEOUT_3CYC = 0,
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TIMEOUT_7CYC = 1,
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TIMEOUT_11CYC = 2,
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TIMEOUT_15CYC = 3,
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TIMEOUT_19CYC = 4,
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TIMEOUT_23CYC = 5,
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TIMEOUT_27CYC = 6,
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TIMEOUT_31CYC = 7,
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TIMEOUT_35CYC = 8,
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TIMEOUT_39CYC = 9,
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TIMEOUT_43CYC = 10,
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TIMEOUT_47CYC = 11,
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TIMEOUT_51CYC = 12,
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TIMEOUT_55CYC = 13,
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TIMEOUT_59CYC = 14,
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TIMEOUT_63CYC = 15,
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};
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timer_counter_control_t timer_counter_control;
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};
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class adf4001_ctrl
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{
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public:
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adf4001_ctrl(uhd::spi_iface::sptr _spi, int slaveno);
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virtual ~adf4001_ctrl() = default;
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virtual void set_lock_to_ext_ref(bool external);
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private:
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uhd::spi_iface::sptr spi_iface;
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int slaveno;
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spi_config_t spi_config;
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adf4001_regs_t adf4001_regs;
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void program_regs(void);
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void write_reg(uint8_t addr);
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};
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}} // namespace uhd::usrp
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