uhd/.ci/templates/job-uhd-streaming-tests-beauty.yml
2025-12-15 09:53:39 +01:00

134 lines
3.9 KiB
YAML

parameters:
- name: uhdSrcDir
type: string
- name: uhdArtifactSource
type: string
default: current
- name: uhdFpgaArtifactSource
type: string
default: current
- name: testLength
type: string
- name: dpdkDirs
type: object
default:
- '/opt/dpdk-19.11'
- '/opt/dpdk-23.11'
jobs:
- template: job-uhd-streaming-tests.yml
parameters:
suiteName: 'beauty'
testLength: '${{ parameters.testLength }}'
toolset: 'make'
uhdSrcDir: '${{ parameters.uhdSrcDir }}'
uhdArtifactSource: ${{ parameters.uhdArtifactSource }}
uhdFpgaArtifactSource: '${{ parameters.uhdFpgaArtifactSource }}'
dpdkDirs: '${{ parameters.dpdkDirs }}'
dutMatrix:
# beauty-N320-0 XG:
# dutName: 'beauty-N320-0'
# dutType: 'N320'
# dutAddr: '192.168.10.4'
# dutSecondAddr: '192.168.20.4'
# dutFPGA: 'XG'
# dutNameId: ''
# dutNumRecvFrames: ''
# dutNumSendFrames: ''
beauty-X310-0:
dutName: 'beauty-X310-0'
dutType: 'x310'
dutAddr: '$(x310_dutAddr)'
dutSecondAddr: '$(x310_dutSecondAddr)'
dutFPGA: 'XG'
dutNameId: ''
dutNumRecvFrames: ''
dutNumSendFrames: ''
jtagSerial: '$(x310_jtagSerial)'
sfpInt0: '$(x310_sfpInt0)'
sfpInt1: '$(x310_sfpInt1)'
# beauty-X410-0 X4_200:
# dutName: 'beauty-X410-0'
# dutFamily: 'x4xx'
# dutType: 'x410'
# dutAddr: '$(x410_dutAddr)'
# dutSecondAddr: '$(x410_dutSecondAddr)'
# dutFPGA:'X4_200'
# dutNameId: ''
# dutEmbeddedImagesArtifact: 'x4xx-images'
# uartSerial: '$(x410_uartSerial)'
# dutNumRecvFrames: ''
# dutNumSendFrames: ''
# sfpInt0: '$(x410_sfpInt0)'
# sfpInt1: '$(x410_sfpInt1)'
beauty-X410-0 CG_400:
dutName: 'beauty-X410-0'
dutFamily: 'x4xx'
dutType: 'x410'
dutAddr: '$(x410_dutAddr)'
dutSecondAddr: '$(x410_dutSecondAddr)'
dutFPGA: 'CG_400'
dutNameId: ''
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '$(x410_uartSerial)'
dutNumRecvFrames: ''
dutNumSendFrames: ''
sfpInt0: '$(x410_sfpInt0)'
sfpInt1: '$(x410_sfpInt1)'
beauty-X410-0 UC_200:
dutName: 'beauty-X410-0'
dutFamily: 'x4xx'
dutType: 'x410'
# UC image: device is reachable only via dutSecondAddr
dutAddr: '$(x410_dutSecondAddr)'
dutSecondAddr: '$(x410_dutSecondAddr)'
dutFPGA: 'UC_200'
dutNameId: ''
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '$(x410_uartSerial)'
dutNumRecvFrames: ''
dutNumSendFrames: ''
sfpInt0: '$(x410_sfpInt0)'
sfpInt1: '$(x410_sfpInt1)'
# beauty-E320-0:
# dutName: 'beauty-E320-0'
# dutType: 'E320'
# dutAddr: '192.168.10.5'
# dutSecondAddr: ''
# dutFPGA: 'XG'
# dutNameId: ''
# dutNumRecvFrames: ''
# dutNumSendFrames: ''
# beauty-N310-0:
# dutName: 'beauty-N310-0'
# dutType: 'N310'
# dutAddr: '192.168.10.6'
# dutSecondAddr: '192.168.20.6'
# dutFPGA: 'XG'
# dutNameId: ''
# dutNumRecvFrames: ''
# dutNumSendFrames: ''
# beauty-X310_TwinRx-0:
# dutName: 'beauty-X310_TwinRx-0'
# dutType: 'X310_TwinRx'
# dutAddr: '192.168.10.7'
# dutSecondAddr: '192.168.20.7'
# dutFPGA: 'XG'
# dutNameId: ''
# dutNumRecvFrames: ''
# dutNumSendFrames: ''
# sfpInt0: 'ens4f0'
# sfpInt1: 'ens4f1'
# beauty-B210-0:
# dutName: 'beauty-B210-0'
# dutFamily: 'b200'
# dutType: 'B210'
# dutAddr: ''
# dutSecondAddr: ''
# dutFPGA: ''
# dutNameId: 'MyB210'
# dutNumRecvFrames: '256'
# dutNumSendFrames: '256'
# dutGetFpgaImagesMethod: 'uhd_images_downloader'