The RFNoC DDC/DUC block controllers had a bug, in which they would only
program the upper 24 bits of the 32-bit phase increment value for the
digital frequency shifter.
The DDC/DUC use a 24-bit DDS + multiplier to shift frequency digitally,
but the phase increment input to the DDS is a 32-bit value, which we
were (incorrectly) quantizing to a 24-bit value. This meant we were
artificially limiting the digital frequency accuracy, e.g., for a 200
MHz sample clock, to 200MHz / 2^{24} == (approx.) 12 Hz, which in turn
meant there was an unnecessary frequency error of up to 6 Hz (for lower
clock rates, the error would be smaller but still unnecessarily high).
This patch fixes the width of the phase increment value and allows for
sub-Hz accuracy (once again).
This bug was introduced in 699870d (first released with UHD 4.2).
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