From fa7c3604c4ccbae47a972b9e84e66aa6d9393032 Mon Sep 17 00:00:00 2001 From: turcofran Date: Fri, 23 Jan 2026 17:02:29 +0000 Subject: [PATCH] fpga: make: Use a resources file for RFNOC_OOT_SRCS Use a resources file to pass RFNoC OOT source files to Vivado TCL scripts, avoiding ARG_MAX argument list limits. Co-authored-by: Martin Braun --- fpga/usrp3/tools/make/viv_design_builder.mak | 6 ++++++ fpga/usrp3/tools/scripts/viv_utils.tcl | 14 ++++++++++++++ fpga/usrp3/top/e31x/Makefile.e31x.inc | 6 ++++-- fpga/usrp3/top/e320/Makefile.e320.inc | 8 +++++--- fpga/usrp3/top/n3xx/Makefile.n3xx.inc | 9 ++++++--- fpga/usrp3/top/x300/Makefile.x300.inc | 9 ++++++--- fpga/usrp3/top/x400/Makefile.x4xx.inc | 9 ++++++--- 7 files changed, 47 insertions(+), 14 deletions(-) diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak index dd851f21a..04fe00e46 100644 --- a/fpga/usrp3/tools/make/viv_design_builder.mak +++ b/fpga/usrp3/tools/make/viv_design_builder.mak @@ -29,6 +29,7 @@ BUILD_VIVADO_DESIGN = \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_PROJECT=$(VIVADO_PROJECT); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \ + export VIV_OOT_SRCS_FILE=$(OOT_SRCS_FILE); \ export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \ export VIV_INCR_BUILD=$(INCR_BUILD); \ export VIV_SECURE_KEY=$(call RESOLVE_PATH,$(abspath $(SECURE_KEY))); \ @@ -56,6 +57,7 @@ CHECK_VIVADO_DESIGN = \ export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \ + export VIV_OOT_SRCS_FILE=$(OOT_SRCS_FILE); \ export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)../../"; \ cd $(BUILD_DIR); \ $(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(TOOLS_DIR)/scripts/check_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou @@ -63,3 +65,7 @@ CHECK_VIVADO_DESIGN = \ # Predeclare RFNOC_OOT_SRCS to make sure it's not recursively expanded RFNOC_OOT_SRCS := + +# Out-of-tree sources file generation (shared by all platforms) +# Note: The target rule for this file must be defined after RFNOC_OOT_SRCS is populated +OOT_SRCS_FILE := $(BUILD_DIR)/rfnoc_oot.srcs diff --git a/fpga/usrp3/tools/scripts/viv_utils.tcl b/fpga/usrp3/tools/scripts/viv_utils.tcl index 802b8ffa1..84a203082 100644 --- a/fpga/usrp3/tools/scripts/viv_utils.tcl +++ b/fpga/usrp3/tools/scripts/viv_utils.tcl @@ -28,6 +28,7 @@ namespace eval ::vivado_utils { variable g_part_name $::env(VIV_PART_NAME) variable g_output_dir $::env(VIV_OUTPUT_DIR) variable g_source_files $::env(VIV_DESIGN_SRCS) + variable g_oot_srcs_file $::env(VIV_OOT_SRCS_FILE) variable g_vivado_mode $::env(VIV_MODE) variable g_project_save $::env(VIV_PROJECT) variable g_secure_key $::env(VIV_SECURE_KEY) @@ -51,6 +52,7 @@ proc ::vivado_utils::initialize_project { {save_to_disk 0} } { variable g_part_name variable g_output_dir variable g_source_files + variable g_oot_srcs_file variable g_project_save variable bd_files "" @@ -65,6 +67,18 @@ proc ::vivado_utils::initialize_project { {save_to_disk 0} } { create_project -in_memory -part $g_part_name } + # Get OOT sources from resources file to avoid ARG_MAX issue + if {[info exists g_oot_srcs_file] && [file exists $g_oot_srcs_file]} { + puts "BUILDER: Reading sources from $g_oot_srcs_file" + set fh [open $g_oot_srcs_file r]; + while {[gets $fh line] >= 0} { + if {$line ne ""} { + append g_source_files " " $line + } + } + close $fh + } + # Expand directories to include their contents (needed for HLS outputs) foreach src_file $g_source_files { if [expr [file isdirectory $src_file] == 1] { diff --git a/fpga/usrp3/top/e31x/Makefile.e31x.inc b/fpga/usrp3/top/e31x/Makefile.e31x.inc index 7c51a6caa..690a765aa 100644 --- a/fpga/usrp3/top/e31x/Makefile.e31x.inc +++ b/fpga/usrp3/top/e31x/Makefile.e31x.inc @@ -90,7 +90,6 @@ $(LIB_HLS_IP_SRCS) \ $(EXTRAM_SRCS) \ $(CAP_GEN_GENERIC_SRCS) \ $(RFNOC_SRCS) \ -$(RFNOC_OOT_SRCS)\ $(RFNOC_IMAGE_CORE_SRCS) \ $(TOP_SRCS) \ $(MB_XDC) \ @@ -107,6 +106,9 @@ IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh" VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS) +$(OOT_SRCS_FILE): + @printf "%s\n" $(RFNOC_OOT_SRCS) > $@ + # DESIGN_SRCS and VERILOG_DEFS must be defined bin: .prereqs @echo "Build directory:: $(BUILD_DIR)" @@ -123,4 +125,4 @@ rtl: .prereqs viv_ip: .prereqs $$(DESIGN_SRCS) ip @echo "IP build for $(NAME) DONE . . ." -.PHONY: bin synth rtl viv_ip +.PHONY: bin synth rtl viv_ip $(OOT_SRCS_FILE) diff --git a/fpga/usrp3/top/e320/Makefile.e320.inc b/fpga/usrp3/top/e320/Makefile.e320.inc index 65f4ce75a..6de53872b 100644 --- a/fpga/usrp3/top/e320/Makefile.e320.inc +++ b/fpga/usrp3/top/e320/Makefile.e320.inc @@ -108,7 +108,6 @@ $(LIB_HLS_IP_SRCS) \ $(EXTRAM_SRCS) \ $(CAP_GEN_GENERIC_SRCS) \ $(RFNOC_SRCS) \ -$(RFNOC_OOT_SRCS) \ $(RFNOC_XPORT_SV_SRCS) \ $(RFNOC_IMAGE_CORE_SRCS) \ $(TOP_SRCS) \ @@ -124,8 +123,11 @@ IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh" VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS) +$(OOT_SRCS_FILE): + @printf "%s\n" $(RFNOC_OOT_SRCS) > $@ + # DESIGN_SRCS and VERILOG_DEFS must be defined -bin: .prereqs +bin: .prereqs $(OOT_SRCS_FILE) @echo "Build directory:: $(BUILD_DIR)" @echo "Printing MB_XDC:: $(MB_XDC)" @echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)" @@ -140,4 +142,4 @@ rtl: .prereqs viv_ip: .prereqs $$(DESIGN_SRCS) ip @echo "IP build for $(NAME) DONE . . ." -.PHONY: bin synth rtl viv_ip +.PHONY: bin synth rtl viv_ip $(OOT_SRCS_FILE) diff --git a/fpga/usrp3/top/n3xx/Makefile.n3xx.inc b/fpga/usrp3/top/n3xx/Makefile.n3xx.inc index 90a375b8f..99279174f 100644 --- a/fpga/usrp3/top/n3xx/Makefile.n3xx.inc +++ b/fpga/usrp3/top/n3xx/Makefile.n3xx.inc @@ -128,7 +128,7 @@ $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(AURORA_PHY_SRCS) \ $(TEN_GIGE_PHY_SRCS) $(ONE_GIGE_PHY_SRCS) \ $(RFNOC_FRAMEWORK_SRCS) $(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \ $(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \ -$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) \ +$(RFNOC_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) \ $(WHITE_RABBIT_SRCS) \ $(RFNOC_XPORT_SV_SRCS) \ $(RFNOC_IMAGE_CORE_SRCS) \ @@ -146,8 +146,11 @@ IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh" VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS) +$(OOT_SRCS_FILE): + @printf "%s\n" $(RFNOC_OOT_SRCS) > $@ + # DESIGN_SRCS and VERILOG_DEFS must be defined -bin: .prereqs +bin: .prereqs $(OOT_SRCS_FILE) @echo "Build directory:: $(BUILD_DIR)" @echo "Printing MB_XDC:: $(MB_XDC)" @echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)" @@ -162,4 +165,4 @@ rtl: .prereqs viv_ip: .prereqs $$(DESIGN_SRCS) ip @echo "IP build for $(NAME) DONE . . ." -.PHONY: bin synth rtl viv_ip +.PHONY: bin synth rtl viv_ip $(OOT_SRCS_FILE) diff --git a/fpga/usrp3/top/x300/Makefile.x300.inc b/fpga/usrp3/top/x300/Makefile.x300.inc index 2c4d88ca0..35f3ecc62 100644 --- a/fpga/usrp3/top/x300/Makefile.x300.inc +++ b/fpga/usrp3/top/x300/Makefile.x300.inc @@ -104,7 +104,7 @@ $(IOPORT2_SRCS) \ $(RFNOC_FRAMEWORK_SRCS) $(PACKET_PROC_SRCS) $(DSP_SRCS) \ $(AXI_SRCS) $(AXI4S_SV_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \ $(LIB_IP_XCI_SRCS) \ -$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) \ +$(RFNOC_SRCS) \ $(RFNOC_XPORT_SV_SRCS) \ $(RFNOC_IMAGE_CORE_SRCS) \ $(TOP_SRCS) $(SFP_SERDES_SRCS) $(DRAM_SRCS) \ @@ -121,8 +121,11 @@ IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh" VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS) +$(OOT_SRCS_FILE): + @printf "%s\n" $(RFNOC_OOT_SRCS) > $@ + # DESIGN_SRCS and VERILOG_DEFS must be defined -bin: .prereqs +bin: .prereqs $(OOT_SRCS_FILE) @echo "Build directory:: $(BUILD_DIR)" @echo "Printing MB_XDC:: $(MB_XDC)" @echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)" @@ -137,4 +140,4 @@ rtl: .prereqs viv_ip: .prereqs $$(DESIGN_SRCS) ip @echo "IP build for $(NAME) DONE . . ." -.PHONY: bin synth rtl viv_ip +.PHONY: bin synth rtl viv_ip $(OOT_SRCS_FILE) diff --git a/fpga/usrp3/top/x400/Makefile.x4xx.inc b/fpga/usrp3/top/x400/Makefile.x4xx.inc index 62e830f40..aec00a63b 100644 --- a/fpga/usrp3/top/x400/Makefile.x4xx.inc +++ b/fpga/usrp3/top/x400/Makefile.x4xx.inc @@ -154,7 +154,7 @@ $(XGE_PCS_PMA_SRCS) \ $(RFNOC_FRAMEWORK_SRCS) $(PACKET_PROC_SRCS) $(VITA_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \ $(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \ $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) $(LIBCOREGEN_SRCS) $(WB_SPI_SRCS) \ -$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) \ +$(RFNOC_SRCS) \ $(RFNOC_XPORT_SV_SRCS) $(RFNOC_IMAGE_CORE_SRCS) \ $(DB_COMMON_SRCS) $(TOP_SRCS) \ ) @@ -170,11 +170,14 @@ IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh" VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS) +$(OOT_SRCS_FILE): + @printf "%s\n" $(RFNOC_OOT_SRCS) > $@ + show-var: @echo "IP_BUILD_DIR: $(IP_BUILD_DIR)" # DESIGN_SRCS and VERILOG_DEFS must be defined -bin: .prereqs +bin: .prereqs $(OOT_SRCS_FILE) @echo "Build directory:: $(BUILD_DIR)" @echo "Printing MB_XDC:: $(MB_XDC)" @echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)" @@ -192,4 +195,4 @@ viv_ip: show-var .prereqs $$(DESIGN_SRCS) ip secure_core: .prereqs $(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_secure_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) -.PHONY: bin synth rtl viv_ip secure_synth_netlist +.PHONY: bin synth rtl viv_ip secure_synth_netlist $(OOT_SRCS_FILE)