diff --git a/fpga/usrp3/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl b/fpga/usrp3/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl
index f35b5c011..b34c26d8b 100644
--- a/fpga/usrp3/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl
+++ b/fpga/usrp3/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl
@@ -20,12 +20,18 @@ set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
-set scripts_vivado_version 2021.1
+set scripts_vivado_version 2025.2
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
- catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+ if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
+
+ } else {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ }
return 1
}
@@ -43,7 +49,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
- create_project project_1 myproj -part xc7z020clg484-1
+ create_project project_1 myproj -part xc7z020clg484-3
}
@@ -287,382 +293,385 @@ proc create_root_design { parentCell } {
# Create instance: s00_width_conv, and set properties
set s00_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s00_width_conv ]
- set_property -dict [ list \
- CONFIG.ACLK_ASYNC {1} \
- CONFIG.FIFO_MODE {2} \
- CONFIG.MI_DATA_WIDTH {128} \
- CONFIG.SI_DATA_WIDTH {64} \
- CONFIG.SYNCHRONIZATION_STAGES {2} \
- ] $s00_width_conv
+ set_property -dict [list \
+ CONFIG.ACLK_ASYNC {1} \
+ CONFIG.FIFO_MODE {2} \
+ CONFIG.MI_DATA_WIDTH {128} \
+ CONFIG.SI_DATA_WIDTH {64} \
+ CONFIG.SYNCHRONIZATION_STAGES {2} \
+ ] $s00_width_conv
+
# Create instance: s01_width_conv, and set properties
set s01_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s01_width_conv ]
- set_property -dict [ list \
- CONFIG.ACLK_ASYNC {1} \
- CONFIG.FIFO_MODE {2} \
- CONFIG.MI_DATA_WIDTH {128} \
- CONFIG.SI_DATA_WIDTH {64} \
- CONFIG.SYNCHRONIZATION_STAGES {2} \
- ] $s01_width_conv
+ set_property -dict [list \
+ CONFIG.ACLK_ASYNC {1} \
+ CONFIG.FIFO_MODE {2} \
+ CONFIG.MI_DATA_WIDTH {128} \
+ CONFIG.SI_DATA_WIDTH {64} \
+ CONFIG.SYNCHRONIZATION_STAGES {2} \
+ ] $s01_width_conv
+
# Create instance: xbar, and set properties
set xbar [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 xbar ]
- set_property -dict [ list \
- CONFIG.DATA_WIDTH {128} \
- CONFIG.ID_WIDTH {1} \
- CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M00_READ_ISSUING {8} \
- CONFIG.M00_WRITE_ISSUING {8} \
- CONFIG.M01_A00_ADDR_WIDTH {0} \
- CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M01_READ_ISSUING {8} \
- CONFIG.M01_WRITE_ISSUING {8} \
- CONFIG.M02_A00_ADDR_WIDTH {0} \
- CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M02_READ_ISSUING {8} \
- CONFIG.M02_WRITE_ISSUING {8} \
- CONFIG.M03_A00_ADDR_WIDTH {0} \
- CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M03_READ_ISSUING {8} \
- CONFIG.M03_WRITE_ISSUING {8} \
- CONFIG.M04_A00_ADDR_WIDTH {0} \
- CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M04_READ_ISSUING {8} \
- CONFIG.M04_WRITE_ISSUING {8} \
- CONFIG.M05_A00_ADDR_WIDTH {0} \
- CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M05_READ_ISSUING {8} \
- CONFIG.M05_WRITE_ISSUING {8} \
- CONFIG.M06_A00_ADDR_WIDTH {0} \
- CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M06_READ_ISSUING {8} \
- CONFIG.M06_WRITE_ISSUING {8} \
- CONFIG.M07_A00_ADDR_WIDTH {0} \
- CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M07_READ_ISSUING {8} \
- CONFIG.M07_WRITE_ISSUING {8} \
- CONFIG.M08_A00_ADDR_WIDTH {0} \
- CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M08_READ_ISSUING {8} \
- CONFIG.M08_WRITE_ISSUING {8} \
- CONFIG.M09_A00_ADDR_WIDTH {0} \
- CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M09_READ_ISSUING {8} \
- CONFIG.M09_WRITE_ISSUING {8} \
- CONFIG.M10_A00_ADDR_WIDTH {0} \
- CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M10_READ_ISSUING {8} \
- CONFIG.M10_WRITE_ISSUING {8} \
- CONFIG.M11_A00_ADDR_WIDTH {0} \
- CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M11_READ_ISSUING {8} \
- CONFIG.M11_WRITE_ISSUING {8} \
- CONFIG.M12_A00_ADDR_WIDTH {0} \
- CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M12_READ_ISSUING {8} \
- CONFIG.M12_WRITE_ISSUING {8} \
- CONFIG.M13_A00_ADDR_WIDTH {0} \
- CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M13_READ_ISSUING {8} \
- CONFIG.M13_WRITE_ISSUING {8} \
- CONFIG.M14_A00_ADDR_WIDTH {0} \
- CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M14_READ_ISSUING {8} \
- CONFIG.M14_WRITE_ISSUING {8} \
- CONFIG.M15_A00_ADDR_WIDTH {0} \
- CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \
- CONFIG.M15_READ_ISSUING {8} \
- CONFIG.M15_WRITE_ISSUING {8} \
- CONFIG.NUM_MI {1} \
- CONFIG.NUM_SI {2} \
- CONFIG.S00_READ_ACCEPTANCE {4} \
- CONFIG.S00_WRITE_ACCEPTANCE {4} \
- CONFIG.S01_BASE_ID {0x00000001} \
- CONFIG.S01_READ_ACCEPTANCE {4} \
- CONFIG.S01_WRITE_ACCEPTANCE {4} \
- CONFIG.S02_BASE_ID {0x00000002} \
- CONFIG.S02_READ_ACCEPTANCE {4} \
- CONFIG.S02_WRITE_ACCEPTANCE {4} \
- CONFIG.S03_BASE_ID {0x00000003} \
- CONFIG.S03_READ_ACCEPTANCE {4} \
- CONFIG.S03_WRITE_ACCEPTANCE {4} \
- CONFIG.S04_BASE_ID {0x00000004} \
- CONFIG.S04_READ_ACCEPTANCE {4} \
- CONFIG.S04_WRITE_ACCEPTANCE {4} \
- CONFIG.S05_BASE_ID {0x00000005} \
- CONFIG.S05_READ_ACCEPTANCE {4} \
- CONFIG.S05_WRITE_ACCEPTANCE {4} \
- CONFIG.S06_BASE_ID {0x00000006} \
- CONFIG.S06_READ_ACCEPTANCE {4} \
- CONFIG.S06_WRITE_ACCEPTANCE {4} \
- CONFIG.S07_BASE_ID {0x00000007} \
- CONFIG.S07_READ_ACCEPTANCE {4} \
- CONFIG.S07_WRITE_ACCEPTANCE {4} \
- CONFIG.S08_BASE_ID {0x00000008} \
- CONFIG.S08_READ_ACCEPTANCE {4} \
- CONFIG.S08_WRITE_ACCEPTANCE {4} \
- CONFIG.S09_BASE_ID {0x00000009} \
- CONFIG.S09_READ_ACCEPTANCE {4} \
- CONFIG.S09_WRITE_ACCEPTANCE {4} \
- CONFIG.S10_BASE_ID {0x0000000a} \
- CONFIG.S10_READ_ACCEPTANCE {4} \
- CONFIG.S10_WRITE_ACCEPTANCE {4} \
- CONFIG.S11_BASE_ID {0x0000000b} \
- CONFIG.S11_READ_ACCEPTANCE {4} \
- CONFIG.S11_WRITE_ACCEPTANCE {4} \
- CONFIG.S12_BASE_ID {0x0000000c} \
- CONFIG.S12_READ_ACCEPTANCE {4} \
- CONFIG.S12_WRITE_ACCEPTANCE {4} \
- CONFIG.S13_BASE_ID {0x0000000d} \
- CONFIG.S13_READ_ACCEPTANCE {4} \
- CONFIG.S13_WRITE_ACCEPTANCE {4} \
- CONFIG.S14_BASE_ID {0x0000000e} \
- CONFIG.S14_READ_ACCEPTANCE {4} \
- CONFIG.S14_WRITE_ACCEPTANCE {4} \
- CONFIG.S15_BASE_ID {0x0000000f} \
- CONFIG.S15_READ_ACCEPTANCE {4} \
- CONFIG.S15_WRITE_ACCEPTANCE {4} \
- CONFIG.STRATEGY {2} \
- ] $xbar
+ set_property -dict [list \
+ CONFIG.DATA_WIDTH {128} \
+ CONFIG.ID_WIDTH {1} \
+ CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M00_READ_ISSUING {8} \
+ CONFIG.M00_WRITE_ISSUING {8} \
+ CONFIG.M01_A00_ADDR_WIDTH {0} \
+ CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M01_READ_ISSUING {8} \
+ CONFIG.M01_WRITE_ISSUING {8} \
+ CONFIG.M02_A00_ADDR_WIDTH {0} \
+ CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M02_READ_ISSUING {8} \
+ CONFIG.M02_WRITE_ISSUING {8} \
+ CONFIG.M03_A00_ADDR_WIDTH {0} \
+ CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M03_READ_ISSUING {8} \
+ CONFIG.M03_WRITE_ISSUING {8} \
+ CONFIG.M04_A00_ADDR_WIDTH {0} \
+ CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M04_READ_ISSUING {8} \
+ CONFIG.M04_WRITE_ISSUING {8} \
+ CONFIG.M05_A00_ADDR_WIDTH {0} \
+ CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M05_READ_ISSUING {8} \
+ CONFIG.M05_WRITE_ISSUING {8} \
+ CONFIG.M06_A00_ADDR_WIDTH {0} \
+ CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M06_READ_ISSUING {8} \
+ CONFIG.M06_WRITE_ISSUING {8} \
+ CONFIG.M07_A00_ADDR_WIDTH {0} \
+ CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M07_READ_ISSUING {8} \
+ CONFIG.M07_WRITE_ISSUING {8} \
+ CONFIG.M08_A00_ADDR_WIDTH {0} \
+ CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M08_READ_ISSUING {8} \
+ CONFIG.M08_WRITE_ISSUING {8} \
+ CONFIG.M09_A00_ADDR_WIDTH {0} \
+ CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M09_READ_ISSUING {8} \
+ CONFIG.M09_WRITE_ISSUING {8} \
+ CONFIG.M10_A00_ADDR_WIDTH {0} \
+ CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M10_READ_ISSUING {8} \
+ CONFIG.M10_WRITE_ISSUING {8} \
+ CONFIG.M11_A00_ADDR_WIDTH {0} \
+ CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M11_READ_ISSUING {8} \
+ CONFIG.M11_WRITE_ISSUING {8} \
+ CONFIG.M12_A00_ADDR_WIDTH {0} \
+ CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M12_READ_ISSUING {8} \
+ CONFIG.M12_WRITE_ISSUING {8} \
+ CONFIG.M13_A00_ADDR_WIDTH {0} \
+ CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M13_READ_ISSUING {8} \
+ CONFIG.M13_WRITE_ISSUING {8} \
+ CONFIG.M14_A00_ADDR_WIDTH {0} \
+ CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M14_READ_ISSUING {8} \
+ CONFIG.M14_WRITE_ISSUING {8} \
+ CONFIG.M15_A00_ADDR_WIDTH {0} \
+ CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \
+ CONFIG.M15_READ_ISSUING {8} \
+ CONFIG.M15_WRITE_ISSUING {8} \
+ CONFIG.NUM_MI {1} \
+ CONFIG.NUM_SI {2} \
+ CONFIG.S00_READ_ACCEPTANCE {4} \
+ CONFIG.S00_WRITE_ACCEPTANCE {4} \
+ CONFIG.S01_BASE_ID {0x00000001} \
+ CONFIG.S01_READ_ACCEPTANCE {4} \
+ CONFIG.S01_WRITE_ACCEPTANCE {4} \
+ CONFIG.S02_BASE_ID {0x00000002} \
+ CONFIG.S02_READ_ACCEPTANCE {4} \
+ CONFIG.S02_WRITE_ACCEPTANCE {4} \
+ CONFIG.S03_BASE_ID {0x00000003} \
+ CONFIG.S03_READ_ACCEPTANCE {4} \
+ CONFIG.S03_WRITE_ACCEPTANCE {4} \
+ CONFIG.S04_BASE_ID {0x00000004} \
+ CONFIG.S04_READ_ACCEPTANCE {4} \
+ CONFIG.S04_WRITE_ACCEPTANCE {4} \
+ CONFIG.S05_BASE_ID {0x00000005} \
+ CONFIG.S05_READ_ACCEPTANCE {4} \
+ CONFIG.S05_WRITE_ACCEPTANCE {4} \
+ CONFIG.S06_BASE_ID {0x00000006} \
+ CONFIG.S06_READ_ACCEPTANCE {4} \
+ CONFIG.S06_WRITE_ACCEPTANCE {4} \
+ CONFIG.S07_BASE_ID {0x00000007} \
+ CONFIG.S07_READ_ACCEPTANCE {4} \
+ CONFIG.S07_WRITE_ACCEPTANCE {4} \
+ CONFIG.S08_BASE_ID {0x00000008} \
+ CONFIG.S08_READ_ACCEPTANCE {4} \
+ CONFIG.S08_WRITE_ACCEPTANCE {4} \
+ CONFIG.S09_BASE_ID {0x00000009} \
+ CONFIG.S09_READ_ACCEPTANCE {4} \
+ CONFIG.S09_WRITE_ACCEPTANCE {4} \
+ CONFIG.S10_BASE_ID {0x0000000a} \
+ CONFIG.S10_READ_ACCEPTANCE {4} \
+ CONFIG.S10_WRITE_ACCEPTANCE {4} \
+ CONFIG.S11_BASE_ID {0x0000000b} \
+ CONFIG.S11_READ_ACCEPTANCE {4} \
+ CONFIG.S11_WRITE_ACCEPTANCE {4} \
+ CONFIG.S12_BASE_ID {0x0000000c} \
+ CONFIG.S12_READ_ACCEPTANCE {4} \
+ CONFIG.S12_WRITE_ACCEPTANCE {4} \
+ CONFIG.S13_BASE_ID {0x0000000d} \
+ CONFIG.S13_READ_ACCEPTANCE {4} \
+ CONFIG.S13_WRITE_ACCEPTANCE {4} \
+ CONFIG.S14_BASE_ID {0x0000000e} \
+ CONFIG.S14_READ_ACCEPTANCE {4} \
+ CONFIG.S14_WRITE_ACCEPTANCE {4} \
+ CONFIG.S15_BASE_ID {0x0000000f} \
+ CONFIG.S15_READ_ACCEPTANCE {4} \
+ CONFIG.S15_WRITE_ACCEPTANCE {4} \
+ CONFIG.STRATEGY {2} \
+ ] $xbar
+
# Create interface connections
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports S00_AXI] [get_bd_intf_pins s00_width_conv/S_AXI]
@@ -672,12 +681,22 @@ proc create_root_design { parentCell } {
connect_bd_intf_net -intf_net xbar_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins xbar/M00_AXI]
# Create port connections
- connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] [get_bd_pins s00_width_conv/m_axi_aclk] [get_bd_pins s01_width_conv/m_axi_aclk] [get_bd_pins xbar/aclk]
- connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] [get_bd_pins s00_width_conv/m_axi_aresetn] [get_bd_pins s01_width_conv/m_axi_aresetn] [get_bd_pins xbar/aresetn]
- connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] [get_bd_pins s00_width_conv/s_axi_aclk]
- connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] [get_bd_pins s00_width_conv/s_axi_aresetn]
- connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] [get_bd_pins s01_width_conv/s_axi_aclk]
- connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] [get_bd_pins s01_width_conv/s_axi_aresetn]
+ connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] \
+ [get_bd_pins s00_width_conv/m_axi_aclk] \
+ [get_bd_pins s01_width_conv/m_axi_aclk] \
+ [get_bd_pins xbar/aclk]
+ connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] \
+ [get_bd_pins s00_width_conv/m_axi_aresetn] \
+ [get_bd_pins s01_width_conv/m_axi_aresetn] \
+ [get_bd_pins xbar/aresetn]
+ connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] \
+ [get_bd_pins s00_width_conv/s_axi_aclk]
+ connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] \
+ [get_bd_pins s00_width_conv/s_axi_aresetn]
+ connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] \
+ [get_bd_pins s01_width_conv/s_axi_aclk]
+ connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] \
+ [get_bd_pins s01_width_conv/s_axi_aresetn]
# Create address segments
assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] -force
diff --git a/fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci b/fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci
index 7d467a859..283660c5b 100644
--- a/fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci
+++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci
@@ -1,2649 +1,1680 @@
-
-
- xilinx.com
- xci
- unknown
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+ "NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "AWID": [ { "physical_name": "s_axi_awid" } ],
+ "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+ "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+ "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+ "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+ "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+ "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+ "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+ "AWQOS": [ { "physical_name": "s_axi_awqos" } ],
+ "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+ "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+ "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+ "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+ "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+ "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+ "WREADY": [ { "physical_name": "s_axi_wready" } ],
+ "BREADY": [ { "physical_name": "s_axi_bready" } ],
+ "BID": [ { "physical_name": "s_axi_bid" } ],
+ "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+ "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+ "ARID": [ { "physical_name": "s_axi_arid" } ],
+ "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+ "ARLEN": [ { "physical_name": "s_axi_arlen" } ],
+ "ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
+ "ARBURST": [ { "physical_name": "s_axi_arburst" } ],
+ "ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
+ "ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
+ "ARPROT": [ { "physical_name": "s_axi_arprot" } ],
+ "ARQOS": [ { "physical_name": "s_axi_arqos" } ],
+ "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+ "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+ "RREADY": [ { "physical_name": "s_axi_rready" } ],
+ "RID": [ { "physical_name": "s_axi_rid" } ],
+ "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+ "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+ "RLAST": [ { "physical_name": "s_axi_rlast" } ],
+ "RVALID": [ { "physical_name": "s_axi_rvalid" } ]
+ }
+ },
+ "SYS_CLK_I": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK": [ { "physical_name": "sys_clk_i" } ]
+ }
+ },
+ "ARESETN": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "ARESETN": [ { "physical_name": "aresetn" } ]
+ }
+ },
+ "C0_ARESETN": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ }
+ },
+ "C1_ARESETN": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ }
+ },
+ "C2_ARESETN": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ }
+ },
+ "C3_ARESETN": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ }
+ },
+ "C4_ARESETN": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ }
+ },
+ "C5_ARESETN": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ }
+ },
+ "C6_ARESETN": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ }
+ },
+ "C7_ARESETN": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ }
+ }
+ },
+ "memory_maps": {
+ "memmap": {
+ "address_blocks": {
+ "memaddr": {
+ "base_address": "0",
+ "range": "536870912",
+ "usage": "memory",
+ "access": "read-write"
+ }
+ }
+ }
+ }
+ }
+ },
+ "checksum": "c859cf5c"
+}
\ No newline at end of file
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl
index eedc169e2..81eeacc9c 100644
--- a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl
@@ -20,12 +20,18 @@ set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
-set scripts_vivado_version 2021.1
+set scripts_vivado_version 2025.2
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
- catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+ if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
+
+ } else {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ }
return 1
}
@@ -216,30 +222,27 @@ proc create_hier_cell_dma { parentCell nameHier } {
# Create instance: axi_dma_eth_internal, and set properties
set axi_dma_eth_internal [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_eth_internal ]
- set_property -dict [ list \
- CONFIG.c_enable_multi_channel {0} \
- CONFIG.c_include_mm2s_dre {1} \
- CONFIG.c_include_s2mm_dre {1} \
- CONFIG.c_m_axi_mm2s_data_width {64} \
- CONFIG.c_m_axis_mm2s_tdata_width {64} \
- CONFIG.c_mm2s_burst_size {16} \
- CONFIG.c_num_mm2s_channels {1} \
- CONFIG.c_num_s2mm_channels {1} \
- CONFIG.c_s2mm_burst_size {16} \
- CONFIG.c_sg_include_stscntrl_strm {0} \
- ] $axi_dma_eth_internal
+ set_property -dict [list \
+ CONFIG.c_enable_multi_channel {0} \
+ CONFIG.c_include_mm2s_dre {1} \
+ CONFIG.c_include_s2mm_dre {1} \
+ CONFIG.c_m_axi_mm2s_data_width {64} \
+ CONFIG.c_m_axis_mm2s_tdata_width {64} \
+ CONFIG.c_mm2s_burst_size {16} \
+ CONFIG.c_s2mm_burst_size {16} \
+ CONFIG.c_sg_include_stscntrl_strm {0} \
+ ] $axi_dma_eth_internal
+
# Create instance: axi_protocol_convert_rx, and set properties
set axi_protocol_convert_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_rx ]
- set_property -dict [ list \
- CONFIG.TRANSLATION_MODE {0} \
- ] $axi_protocol_convert_rx
+ set_property CONFIG.TRANSLATION_MODE {0} $axi_protocol_convert_rx
+
# Create instance: axi_protocol_convert_tx, and set properties
set axi_protocol_convert_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_tx ]
- set_property -dict [ list \
- CONFIG.TRANSLATION_MODE {0} \
- ] $axi_protocol_convert_tx
+ set_property CONFIG.TRANSLATION_MODE {0} $axi_protocol_convert_tx
+
# Create interface connections
connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins m_axis_dma] [get_bd_intf_pins axi_dma_eth_internal/M_AXIS_MM2S]
@@ -252,13 +255,24 @@ proc create_hier_cell_dma { parentCell nameHier } {
connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_pins s_axis_dma] [get_bd_intf_pins axi_dma_eth_internal/S_AXIS_S2MM]
# Create port connections
- connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins tx_irq] [get_bd_pins axi_dma_eth_internal/mm2s_introut]
- connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins rx_irq] [get_bd_pins axi_dma_eth_internal/s2mm_introut]
- connect_bd_net -net axi_dma_0_s2mm_prmry_reset_out_n [get_bd_pins axi_dma_eth_internal/s2mm_prmry_reset_out_n] [get_bd_pins axi_protocol_convert_rx/aresetn]
- connect_bd_net -net axi_dma_eth_internal_mm2s_prmry_reset_out_n [get_bd_pins axi_dma_eth_internal/mm2s_prmry_reset_out_n] [get_bd_pins axi_protocol_convert_tx/aresetn]
- connect_bd_net -net bus_clk_1 [get_bd_pins bus_clk] [get_bd_pins axi_dma_eth_internal/m_axi_mm2s_aclk] [get_bd_pins axi_dma_eth_internal/m_axi_s2mm_aclk] [get_bd_pins axi_dma_eth_internal/m_axi_sg_aclk] [get_bd_pins axi_protocol_convert_rx/aclk] [get_bd_pins axi_protocol_convert_tx/aclk]
- connect_bd_net -net clk40_1 [get_bd_pins clk40] [get_bd_pins axi_dma_eth_internal/s_axi_lite_aclk]
- connect_bd_net -net clk40_rstn_1 [get_bd_pins clk40_rstn] [get_bd_pins axi_dma_eth_internal/axi_resetn]
+ connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_eth_internal/mm2s_introut] \
+ [get_bd_pins tx_irq]
+ connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_eth_internal/s2mm_introut] \
+ [get_bd_pins rx_irq]
+ connect_bd_net -net axi_dma_0_s2mm_prmry_reset_out_n [get_bd_pins axi_dma_eth_internal/s2mm_prmry_reset_out_n] \
+ [get_bd_pins axi_protocol_convert_rx/aresetn]
+ connect_bd_net -net axi_dma_eth_internal_mm2s_prmry_reset_out_n [get_bd_pins axi_dma_eth_internal/mm2s_prmry_reset_out_n] \
+ [get_bd_pins axi_protocol_convert_tx/aresetn]
+ connect_bd_net -net bus_clk_1 [get_bd_pins bus_clk] \
+ [get_bd_pins axi_dma_eth_internal/m_axi_sg_aclk] \
+ [get_bd_pins axi_dma_eth_internal/m_axi_mm2s_aclk] \
+ [get_bd_pins axi_dma_eth_internal/m_axi_s2mm_aclk] \
+ [get_bd_pins axi_protocol_convert_rx/aclk] \
+ [get_bd_pins axi_protocol_convert_tx/aclk]
+ connect_bd_net -net clk40_1 [get_bd_pins clk40] \
+ [get_bd_pins axi_dma_eth_internal/s_axi_lite_aclk]
+ connect_bd_net -net clk40_rstn_1 [get_bd_pins clk40_rstn] \
+ [get_bd_pins axi_dma_eth_internal/axi_resetn]
# Restore current instance
current_bd_instance $oldCurInst
@@ -437,463 +451,337 @@ proc create_root_design { parentCell } {
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
- set_property -dict [ list \
- CONFIG.ENABLE_ADVANCED_OPTIONS {0} \
- CONFIG.NUM_MI {4} \
- ] $axi_interconnect_0
+ set_property -dict [list \
+ CONFIG.ENABLE_ADVANCED_OPTIONS {0} \
+ CONFIG.NUM_MI {4} \
+ ] $axi_interconnect_0
+
# Create instance: dma
create_hier_cell_dma [current_bd_instance .] dma
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
- set_property -dict [ list \
- CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {866.666687} \
- CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
- CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
- CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {40.000000} \
- CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {166.666672} \
- CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \
- CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \
- CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {144.444443} \
- CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {144.444443} \
- CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {144.444443} \
- CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {144.444443} \
- CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {144.444443} \
- CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {144.444443} \
- CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
- CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {144.444443} \
- CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {1000} \
- CONFIG.PCW_ARMPLL_CTRL_FBDIV {52} \
- CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_CLK0_FREQ {100000000} \
- CONFIG.PCW_CLK1_FREQ {40000000} \
- CONFIG.PCW_CLK2_FREQ {166666672} \
- CONFIG.PCW_CLK3_FREQ {200000000} \
- CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1733.333} \
- CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
- CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
- CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
- CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
- CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
- CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
- CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
- CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
- CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
- CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
- CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {16} \
- CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
- CONFIG.PCW_ENET0_RESET_ENABLE {1} \
- CONFIG.PCW_ENET0_RESET_IO {MIO 11} \
- CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_ENET1_RESET_ENABLE {0} \
- CONFIG.PCW_ENET_RESET_ENABLE {1} \
- CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
- CONFIG.PCW_EN_CLK1_PORT {1} \
- CONFIG.PCW_EN_CLK2_PORT {1} \
- CONFIG.PCW_EN_CLK3_PORT {1} \
- CONFIG.PCW_EN_EMIO_ENET0 {0} \
- CONFIG.PCW_EN_EMIO_GPIO {1} \
- CONFIG.PCW_EN_EMIO_I2C1 {0} \
- CONFIG.PCW_EN_EMIO_PJTAG {0} \
- CONFIG.PCW_EN_EMIO_SPI0 {1} \
- CONFIG.PCW_EN_EMIO_SPI1 {1} \
- CONFIG.PCW_EN_EMIO_UART0 {0} \
- CONFIG.PCW_EN_ENET0 {1} \
- CONFIG.PCW_EN_GPIO {1} \
- CONFIG.PCW_EN_I2C0 {1} \
- CONFIG.PCW_EN_I2C1 {0} \
- CONFIG.PCW_EN_PJTAG {0} \
- CONFIG.PCW_EN_RST1_PORT {0} \
- CONFIG.PCW_EN_RST2_PORT {0} \
- CONFIG.PCW_EN_RST3_PORT {0} \
- CONFIG.PCW_EN_SDIO0 {1} \
- CONFIG.PCW_EN_SPI0 {1} \
- CONFIG.PCW_EN_SPI1 {1} \
- CONFIG.PCW_EN_UART0 {1} \
- CONFIG.PCW_EN_UART1 {1} \
- CONFIG.PCW_EN_USB0 {1} \
- CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
- CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
- CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {10} \
- CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \
- CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {4} \
- CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {3} \
- CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {5} \
- CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {2} \
- CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \
- CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \
- CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \
- CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
- CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {40} \
- CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {166.6667} \
- CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \
- CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
- CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \
- CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \
- CONFIG.PCW_FPGA_FCLK3_ENABLE {1} \
- CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
- CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \
- CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
- CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
- CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
- CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
- CONFIG.PCW_I2C0_I2C0_IO {MIO 46 .. 47} \
- CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_I2C0_RESET_ENABLE {0} \
- CONFIG.PCW_I2C0_RESET_IO {