From dad6f906f912e2cc525c973f3bd3a70b5e2fdf40 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Max=20K=C3=B6hler?= Date: Tue, 29 Sep 2026 14:53:11 +0200 Subject: [PATCH] fpga: remove X420 variants without DDC/DUC --- .ci/templates/stages-uhd-pipeline.yml | 27 +--- .ci/uhd-pipeline-pr.yml | 7 - .ci/uhd-pipeline.yml | 5 - .../x420_CG_1000_woDDC_rfnoc_image_core.yml | 133 ------------------ .../x420_CG_400_woDDC_rfnoc_image_core.yml | 20 --- 5 files changed, 1 insertion(+), 191 deletions(-) delete mode 100644 fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml delete mode 100644 fpga/usrp3/top/x400/x420_CG_400_woDDC_rfnoc_image_core.yml diff --git a/.ci/templates/stages-uhd-pipeline.yml b/.ci/templates/stages-uhd-pipeline.yml index d13ae4c7a..76f248bf9 100644 --- a/.ci/templates/stages-uhd-pipeline.yml +++ b/.ci/templates/stages-uhd-pipeline.yml @@ -257,10 +257,6 @@ parameters: timeout: 720 attempt_timeout: 360 max_attempts: 2 -- name: use_low_success_fpga_targets - type: boolean - displayName: Force use of FPGA with low-success compile rates - default: true # Next parameters are used to control conditional execution of embedded system image build stages. # They are not parameters that can be set by the user, # but rather they are computed based on the output of the analyze_changeset stage. @@ -786,28 +782,7 @@ stages: package_access: ${{ parameters.package_access }} fpga_imgs_source: ${{ parameters.fpga_imgs_source }} x410_targets_matrix: ${{ parameters.x410_targets_matrix }} - x420_targets_matrix: - ${{ if eq(parameters.use_low_success_fpga_targets, false) }}: - # Keep all X420 targets except X420_CG_1000 and X420_CG_400 - ${{ each pair in parameters.x420_targets_matrix }}: - ${{ if and(ne(pair.key, 'X420_CG_1000'), ne(pair.key, 'X420_CG_400')) }}: - ${{ pair.key }}: ${{ pair.value }} - # Re-add targets with overrides - X420_CG_1000: - ${{ each pair in parameters.x420_targets_matrix.X420_CG_1000 }}: - ${{ if ne(pair.key, 'image_core') }}: - ${{ pair.key }}: ${{ pair.value }} - ${{ else }}: - image_core: x420_CG_1000_woDDC_rfnoc_image_core.yml - X420_CG_400: - ${{ each pair in parameters.x420_targets_matrix.X420_CG_400 }}: - ${{ if ne(pair.key, 'image_core') }}: - ${{ pair.key }}: ${{ pair.value }} - ${{ else }}: - image_core: x420_CG_400_woDDC_rfnoc_image_core.yml - ${{ else }}: - ${{ each pair in parameters.x420_targets_matrix }}: - ${{ pair.key }}: ${{ pair.value }} + x420_targets_matrix: ${{ parameters.x420_targets_matrix }} x440_targets_matrix: ${{ parameters.x440_targets_matrix }} additional_setup_steps: - checkout: rfnoc-oot-blocks diff --git a/.ci/uhd-pipeline-pr.yml b/.ci/uhd-pipeline-pr.yml index eec43a589..2520fb5b6 100644 --- a/.ci/uhd-pipeline-pr.yml +++ b/.ci/uhd-pipeline-pr.yml @@ -135,10 +135,6 @@ parameters: - 'files.ettus.com (Public)' displayName: Published Package Access default: 'Internal' -- name: use_low_success_fpga_targets - type: boolean - displayName: Force use of FPGA with low-success compile rates - default: false - name: selected_streaming_tests type: string displayName: Streaming Tests Multi-Select (comma-separated) @@ -189,8 +185,5 @@ extends: publish_int_files: true package_and_publish_images: ${{ parameters.package_and_publish_images }} package_access: ${{ parameters.package_access }} - use_low_success_fpga_targets: ${{ parameters.use_low_success_fpga_targets }} # Test parameters selected_streaming_tests: ${{ parameters.selected_streaming_tests }} - - \ No newline at end of file diff --git a/.ci/uhd-pipeline.yml b/.ci/uhd-pipeline.yml index 476a1b05e..ace9e12ba 100644 --- a/.ci/uhd-pipeline.yml +++ b/.ci/uhd-pipeline.yml @@ -118,10 +118,6 @@ parameters: - 'files.ettus.com (Public)' displayName: Published Package Access default: 'Internal' -- name: use_low_success_fpga_targets - type: boolean - displayName: Force use of FPGA with low-success compile rates - default: false - name: selected_streaming_tests type: string displayName: Streaming Tests Multi-Select (comma-separated) @@ -169,6 +165,5 @@ extends: publish_int_files: true package_and_publish_images: ${{ parameters.package_and_publish_images }} package_access: ${{ parameters.package_access }} - use_low_success_fpga_targets: ${{ parameters.use_low_success_fpga_targets }} # Test parameters selected_streaming_tests: ${{ parameters.selected_streaming_tests }} diff --git a/fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml deleted file mode 100644 index 3f06b48fc..000000000 --- a/fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml +++ /dev/null @@ -1,133 +0,0 @@ -# General parameters -# ----------------------------------------- -schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file -copyright: >- # Copyright information used in file headers - Copyright 2026 Ettus Research, a National Instruments Brand -license: >- # License information used in file headers - SPDX-License-Identifier: LGPL-3.0-or-later -version: '1.0' # File version -chdr_width: 512 # Bit width of the CHDR bus for this image -device: 'x420' # USRP type -image_core_name: 'usrp_x420_fpga_CG_1000' # Name to use for the generated output files -default_target: 'X420' # Default make target -inherit: - - 'yaml_include/x440_radio_base.yml' - - 'yaml_include/x4xx_cg_base.yml' - -parameters: - ENABLE_DRAM: True - NUM_DRAM_BANKS: 2 - NUM_DRAM_CHANS: 2 - DRAM_WIDTH: 512 - -# A list of all stream endpoints in design -# ---------------------------------------- -stream_endpoints: - ep0: # Stream endpoint name - ctrl: True # Endpoint passes control traffic - data: False # Endpoint has no data interface - buff_size_bytes: 0 # Ingress buffer size for data - ep1: - ctrl: False - data: True - buff_size_bytes: 2097152 - ep2: - ctrl: False - data: True - buff_size_bytes: 2097152 - ep3: - ctrl: False - data: True - buff_size_bytes: 131072 - ep4: - ctrl: False - data: True - buff_size_bytes: 131072 - -# A table of which crossbar routes to include -# ------------------------------------------- -# Rows correspond to input ports and columns correspond to output ports. -# Entering a 1 includes and a 0 removes that route from the crossbar. -crossbar_routes: - # eth0 dma ep1 ep3 - # eth1 ep0 ep2 ep4 - - [ 1, 0, 0, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0) - - [ 0, 1, 0, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 1) - - [ 0, 0, 1, 1, 1, 1, 1, 1 ] # dma - - [ 1, 1, 1, 0, 0, 0, 0, 0 ] # ep0 (control only) - - [ 1, 1, 1, 0, 0, 0, 1, 1 ] # ep1 (radio0.0) - - [ 1, 1, 1, 0, 0, 0, 1, 1 ] # ep2 (radio1.0) - - [ 1, 1, 1, 0, 1, 1, 0, 0 ] # ep3 (replay0.0) - - [ 1, 1, 1, 0, 1, 1, 0, 0 ] # ep4 (replay1.0) - -# A list of all NoC blocks in design -# ---------------------------------- -noc_blocks: - radio0: - block_desc: 'radio.yml' - parameters: - NUM_PORTS: 1 - EN_FIFO_OUT_REG: 1 - CTRL_FIFO_SIZE: 1024 - CTRL_OUT_FIFO_SIZE: 1024 - radio1: - block_desc: 'radio.yml' - parameters: - NUM_PORTS: 1 - EN_FIFO_OUT_REG: 1 - CTRL_FIFO_SIZE: 1024 - CTRL_OUT_FIFO_SIZE: 1024 - replay0: - block_desc: 'replay.yml' - parameters: - NUM_PORTS: 1 - MEM_DATA_W: 512 # has to match DRAM_WIDTH parameter above - MEM_ADDR_W: 32 - replay1: - block_desc: 'replay.yml' - parameters: - NUM_PORTS: 1 - MEM_DATA_W: 512 # has to match DRAM_WIDTH parameter above - MEM_ADDR_W: 32 - -# A list of all static connections in design -# ------------------------------------------ -# Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect -# - srcport = Port on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Port on the destination block to connect -connections: - # RF A:0 TX - - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_0 } - # RF A:0 RX - - { srcblk: radio0, srcport: out_0, dstblk: ep1, dstport: in0 } - # RF B:0 TX - - { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 } - # RF B:0 RX - - { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 } - # Replay Connections - - { srcblk: ep3, srcport: out0, dstblk: replay0, dstport: in_0 } - - { srcblk: replay0, srcport: out_0, dstblk: ep3, dstport: in0 } - - { srcblk: ep4, srcport: out0, dstblk: replay1, dstport: in_0 } - - { srcblk: replay1, srcport: out_0, dstblk: ep4, dstport: in0 } - # - # BSP Connections - - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 } - - { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 } - # Front-Panel GPIO - - { srcblk: _device_, srcport: _none_, dstblk: _device_, dstport: gpio0 } - - { srcblk: _device_, srcport: _none_, dstblk: _device_, dstport: gpio1 } - # Other BSP connections are inherited from YAML include files - -# A list of all clock domain connections in design -# ------------------------------------------------ -# Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device_") -# - srcport = Clock domain on the source block to connect -# - dstblk = Destination block to connect -# - dstport = Clock domain on the destination block to connect -clk_domains: - - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } - - { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem } - # Other clock domains are inherited from YAML include files diff --git a/fpga/usrp3/top/x400/x420_CG_400_woDDC_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_CG_400_woDDC_rfnoc_image_core.yml deleted file mode 100644 index 4f1ef7934..000000000 --- a/fpga/usrp3/top/x400/x420_CG_400_woDDC_rfnoc_image_core.yml +++ /dev/null @@ -1,20 +0,0 @@ -# General parameters -# ----------------------------------------- -schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file -copyright: >- # Copyright information used in file headers - Copyright 2026 Ettus Research, a National Instruments Brand -license: >- # License information used in file headers - SPDX-License-Identifier: LGPL-3.0-or-later -version: '1.0' # File version -chdr_width: 512 # Bit width of the CHDR bus for this image -device: 'x420' # USRP type -image_core_name: 'usrp_x420_fpga_CG_400' # Name to use for the generated output files -default_target: 'X420' # Default make target -# This image is identical to the 1000 MHz image, except for the RF bandwidth, -# which is achieved by adding resamplers with fixed factor of 3 in the RF data -# path -inherit: - - 'x420_CG_1000_woDDC_rfnoc_image_core.yml' - -parameters: - RF_BW: 400