diff --git a/mpm/python/usrp_mpm/components.py b/mpm/python/usrp_mpm/components.py index bb6617f64..9ca204283 100644 --- a/mpm/python/usrp_mpm/components.py +++ b/mpm/python/usrp_mpm/components.py @@ -212,7 +212,7 @@ class ZynqComponents: file_extension = file_extension[1:].lower() updc = self._merge_updateable_components() if file_extension not in updc["fpga"].get("supported_file_extensions", ["bit", "bin"]): - if not self.device_info.get("customizable_fpga", True): + if self.device_info.get("locked_fpga", True): msg = " Please note that only signed bitstreams (.bin files) from official UHD releases are supported." else: msg = "" @@ -229,8 +229,8 @@ class ZynqComponents: fpga_bit_to_bin(filepath, binfile_path, flip=True) elif file_extension == "bin": if self.handle_bootgen_bin_files: - if not self.device_info.get("customizable_fpga", True): - # In case of non-customizable FPGA, verify that .bin file is signed + if self.device_info.get("locked_fpga", False): + # In case of locked FPGA, verify that .bin file is signed self.log.debug("Verifying FPGA bitstream (.bin file)") try: verify(filepath, self.bootgen_arch) diff --git a/mpm/python/usrp_mpm/discovery.py b/mpm/python/usrp_mpm/discovery.py index 3961e37c0..ff0f023fd 100644 --- a/mpm/python/usrp_mpm/discovery.py +++ b/mpm/python/usrp_mpm/discovery.py @@ -60,7 +60,7 @@ def _discovery_process(state, discovery_addr): + [b"serial=" + state.dev_serial.value] + [b"name=" + state.dev_name.value] + [b"fpga=" + state.dev_fpga_type.value] - + [b"customizable_fpga=" + state.dev_customizable_fpga.value] + + [b"locked_fpga=" + state.dev_locked_fpga.value] + [b"rpc_version=" + RPC_VERSION] + [RESPONSE_CLAIMED_KEY + to_binary_str("={}".format(state.claim_status.value))] ) diff --git a/mpm/python/usrp_mpm/mpmtypes.py b/mpm/python/usrp_mpm/mpmtypes.py index b3c748c38..cb03b5f2f 100644 --- a/mpm/python/usrp_mpm/mpmtypes.py +++ b/mpm/python/usrp_mpm/mpmtypes.py @@ -39,4 +39,4 @@ class SharedState: self.dev_name = Array(ctypes.c_char, 21, lock=self.lock) self.dev_product = Array(ctypes.c_char, 16, lock=self.lock) self.dev_fpga_type = Array(ctypes.c_char, 8, lock=self.lock) - self.dev_customizable_fpga = Array(ctypes.c_char, 8, lock=self.lock) + self.dev_locked_fpga = Array(ctypes.c_char, 8, lock=self.lock) diff --git a/mpm/python/usrp_mpm/periph_manager/x4xx.py b/mpm/python/usrp_mpm/periph_manager/x4xx.py index 646d88082..38161bf8b 100644 --- a/mpm/python/usrp_mpm/periph_manager/x4xx.py +++ b/mpm/python/usrp_mpm/periph_manager/x4xx.py @@ -247,9 +247,9 @@ class x4xx(ZynqComponents, PeriphManagerBase): mb_pid = eeprom_md.get("pid") device_info["product"] = cls.pids.get(mb_pid, "unknown") if (mb_pid & 0xF000) == 0x7000: - device_info["customizable_fpga"] = False + device_info["locked_fpga"] = True else: - device_info["customizable_fpga"] = True + device_info["locked_fpga"] = False module_serial = eeprom_md.get("module_serial") if module_serial is not None: device_info["serial"] = module_serial @@ -817,7 +817,7 @@ class x4xx(ZynqComponents, PeriphManagerBase): @no_rpc def _update_fpga_supported_file_extensions(self): """Update the fpga type stored in the updateable components""" - if not self.device_info["customizable_fpga"]: + if self.device_info["locked_fpga"]: # only bin files generated by bootgen with authenticated FPGA partition are supported self.updateable_components["fpga"]["supported_file_extensions"] = ["bin"] diff --git a/mpm/python/usrp_mpm/periph_manager/x4xx_update_cpld.py b/mpm/python/usrp_mpm/periph_manager/x4xx_update_cpld.py index 858092e58..c6a30a9f2 100644 --- a/mpm/python/usrp_mpm/periph_manager/x4xx_update_cpld.py +++ b/mpm/python/usrp_mpm/periph_manager/x4xx_update_cpld.py @@ -289,9 +289,9 @@ def main(): 0x410: "X410", 0x420: "X420", 0x440: "X440", - 0x7410: "X410 (non-customizable FPGA)", - 0x7420: "X420 (non-customizable FPGA)", - 0x7440: "X440 (non-customizable FPGA)", + 0x7410: "X410 (locked FPGA)", + 0x7420: "X420 (locked FPGA)", + 0x7440: "X440 (locked FPGA)", } device = devices.get(pid, "unknown device") parser.epilog = ( diff --git a/mpm/python/usrp_mpm/rpc_server.py b/mpm/python/usrp_mpm/rpc_server.py index 703cb4d42..c438c69c5 100644 --- a/mpm/python/usrp_mpm/rpc_server.py +++ b/mpm/python/usrp_mpm/rpc_server.py @@ -184,8 +184,8 @@ class MPMServer(mpm_server_pb2_grpc.MpmServerServiceServicer): self._state.dev_serial.value = to_binary_str(device_info.get("serial", "n/a")) self._state.dev_name.value = to_binary_str(device_info.get("name", "n/a")) self._state.dev_fpga_type.value = to_binary_str(device_info.get("fpga", "n/a")) - self._state.dev_customizable_fpga.value = to_binary_str( - str(device_info.get("customizable_fpga", "n/a")) + self._state.dev_locked_fpga.value = to_binary_str( + str(device_info.get("locked_fpga", "n/a")) ) self._db_methods = [] self._mb_methods = [] @@ -959,8 +959,8 @@ class MPMServer(mpm_server_pb2_grpc.MpmServerServiceServicer): raise RuntimeError(err_msg) info = self.periph_manager.get_device_info() info["mpm_version"] = "{}.{}".format(*MPM_COMPAT_NUM) - if "customizable_fpga" in info: - info["customizable_fpga"] = str(info["customizable_fpga"]) + if "locked_fpga" in info: + info["locked_fpga"] = str(info["locked_fpga"]) if _is_connection_local(self.client_host): info["connection"] = "local" else: diff --git a/mpm/tools/tlv_eeprom/eeprom-pids.c b/mpm/tools/tlv_eeprom/eeprom-pids.c index f152f8901..751cfb5a2 100644 --- a/mpm/tools/tlv_eeprom/eeprom-pids.c +++ b/mpm/tools/tlv_eeprom/eeprom-pids.c @@ -23,9 +23,9 @@ static struct pid_info pid_list[] = { {0x4006, NULL, "IF Test Manufacturing CCA", 0, NULL}, {0x4007, "fbx", "FBX RF DB", 0, NULL}, {0x4008, "hbx", "HBX RF DB", 0, NULL}, - {0x7410, "x410", "X410 (non-customizable FPGA)", 0, "customizable_fpga=False"}, - {0x7420, "x420", "X420 (non-customizable FPGA)", 0, "customizable_fpga=False"}, - {0x7440, "x440", "X440 (non-customizable FPGA)", 0, "customizable_fpga=False"}, + {0x7410, "x410", "X410 (locked FPGA)", 0, "locked_fpga=True"}, + {0x7420, "x420", "X420 (locked FPGA)", 0, "locked_fpga=True"}, + {0x7440, "x440", "X440 (locked FPGA)", 0, "locked_fpga=True"}, }; #define ARRAY_SIZE(x) (sizeof((x)) / sizeof((*x)))