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ci: fpga: fix build condition for e320 FPGA

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fdietze-ni 2025-08-11 15:12:23 +02:00 committed by mkoop-ni
parent 652108ff95
commit b8bf41c04a
2 changed files with 4 additions and 4 deletions
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2
.ci/fpga/devices/job-build-fpga-e320.yml
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@ -5,7 +5,7 @@
#
# Description:
#
# This template defines a stages-based pipeline for building E32X FPGA targets.
# This template defines a stages-based pipeline for building E320 FPGA targets.
#
# See https://aka.ms/yaml for pipeline YAML documentation.
#

6
fpga/.ci/fpga-pipeline.yml
View File

@ -33,9 +33,9 @@ parameters:
type: boolean
displayName: Build E31x
default: false
- name: build_e32x
- name: build_e320
type: boolean
displayName: Build E32x
displayName: Build E320
default: false
- name: build_x410
type: boolean
@ -150,7 +150,7 @@ extends:
iif(parameters.build_x3x0,'fpga.usrp3.x3xx',''),
iif(parameters.build_n3xx,'fpga.usrp3.n3xx',''),
iif(parameters.build_e31x,'fpga.usrp3.e31x',''),
iif(parameters.build_e32x,'fpga.usrp3.e32x',''),
iif(parameters.build_e320,'fpga.usrp3.e320',''),
iif(parameters.build_x410,'fpga.usrp3.x410',''),
iif(parameters.build_x440,'fpga.usrp3.x440',''),
iif(parameters.build_x4xx_cplds,'fpga.usrp3.cpld.x4xx',''),