mpm: print error if loading FPGA bitstream failed

mpm/python/usrp_mpm/periph_manager/base.py

@@ -20,6 +20,7 @@ from usrp_mpm.mpmutils import get_dboard_class_from_pid
 from usrp_mpm.rpc_utils import no_claim, no_rpc
 from usrp_mpm.sys_utils import dtoverlay, net
 from usrp_mpm.sys_utils.filesystem_status import get_fs_version, get_mender_artifact
+from usrp_mpm.sys_utils.sysfs_fpga_manager import FpgaManager
 from usrp_mpm.sys_utils.udev import (
     get_eeprom_paths,
     get_eeprom_paths_by_symbol,
@@ -242,6 +243,7 @@ class PeriphManagerBase:
         # this is to compare the FPGA compat number with a given compat number
         # that added a feature.
         self.fpga_features = set()
+        self.fpga_manager = FpgaManager()
         self._default_args = ""
         # CHDR transport managers. These need to be instantiated by the child
         # classes.
@@ -591,6 +593,11 @@ class PeriphManagerBase:
         # Need to wait here a second to make sure the ethernet interfaces are up
         # TODO: Fine-tune this number, or wait for some smarter signal.
         sleep(1)
+        fpga_state = self.fpga_manager.get_state()
+        if fpga_state != "operating":
+            msg = f'Failed to apply overlays {requested_overlays}, FPGA is in state "{fpga_state}"'
+            self.log.error(msg)
+            raise RuntimeError(msg)
 
     def _init_dboards(self, dboard_infos, override_dboard_pids, default_args):
         """

mpm/python/usrp_mpm/periph_manager/x4xx.py

@@ -285,6 +285,11 @@ class x4xx(ZynqComponents, PeriphManagerBase):
         # Need to wait here a second to make sure the ethernet interfaces are up
         # TODO: Fine-tune this number, or wait for some smarter signal.
         sleep(1)
+        fpga_state = self.fpga_manager.get_state()
+        if fpga_state != "operating":
+            msg = f'Failed to apply overlays {requested_overlays}, FPGA is in state "{fpga_state}"'
+            self.log.error(msg)
+            raise RuntimeError(msg)
 
     ###########################################################################
     # Ctor and device initialization tasks

mpm/python/usrp_mpm/sys_utils/CMakeLists.txt

@@ -10,6 +10,7 @@ set(USRP_MPM_SYSUTILS_FILES
     ${CMAKE_CURRENT_SOURCE_DIR}/dtoverlay.py
     ${CMAKE_CURRENT_SOURCE_DIR}/i2c_dev.py
     ${CMAKE_CURRENT_SOURCE_DIR}/net.py
+    ${CMAKE_CURRENT_SOURCE_DIR}/sysfs_fpga_manager.py
     ${CMAKE_CURRENT_SOURCE_DIR}/sysfs_gpio.py
     ${CMAKE_CURRENT_SOURCE_DIR}/sysfs_thermal.py
     ${CMAKE_CURRENT_SOURCE_DIR}/udev.py

mpm/python/usrp_mpm/sys_utils/sysfs_fpga_manager.py

@@ -0,0 +1,22 @@
+#
+# Copyright 2017-2026 Ettus Research, A National Instruments Brand
+#
+# SPDX-License-Identifier: GPL-3.0-or-later
+"""Utilty functions for the sysfs fpga_manager API."""
+import pyudev
+
+
+class FpgaManager:
+    """Class representing the fpga_manager class in sysfs."""
+
+    def __init__(self):
+        """Initalize the udev context and find the fpga_manager device."""
+        context = pyudev.Context()
+        self.fpga_manager = [x for x in context.list_devices(subsystem="fpga_manager")][0]
+
+    def get_state(self):
+        """Get the state of the FPGA manager."""
+        with open(self.fpga_manager.sys_path + "/state", "r") as f:
+            state = f.read()
+        # return state without linebreak
+        return state[:-1]