From a76ab6ffc9a8bb78b07d0ece44f579f68c5cc39b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Max=20K=C3=B6hler?= Date: Fri, 4 Sep 2026 12:19:47 +0200 Subject: [PATCH] Revert "ci: usrp4 sim: only run this stage if source is not master" This reverts commit 879ed08bb1887dd1fa917f0bf691ca465e33dc3c. --- .ci/templates/stages-uhd-pipeline.yml | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/.ci/templates/stages-uhd-pipeline.yml b/.ci/templates/stages-uhd-pipeline.yml index 28aa74d58..7cef1e778 100644 --- a/.ci/templates/stages-uhd-pipeline.yml +++ b/.ci/templates/stages-uhd-pipeline.yml @@ -814,16 +814,11 @@ stages: clean: true rfnoc_include_dir: $(Build.SourcesDirectory)/rfnoc-oot-blocks-dev/rfnoc -# We don't want to run this stage on master, because it will always fail due to the check that the hw-tools have implemented. - stage: usrp4_tests displayName: Simulate + Build usrp4-hw dependsOn: analyze_changeset condition: > - and( - succeeded(), - not( - eq(variables['Build.SourceBranch'], 'refs/heads/master') - ), + and(succeeded(), or( contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'fpga.usrp3.x4xx'), contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'fpga.usrp3.all'),