From 9da28f06f704dca454ede0b5f407e5b817f1f1f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Max=20K=C3=B6hler?= Date: Fri, 28 Aug 2026 05:27:27 +0200 Subject: [PATCH] fpga: x420: Use standard ce clock for DDC and DUC blocks for 400 MHz --- .../top/x400/x420_CG_400_rfnoc_image_core.yml | 141 +++++++++++++++- .../top/x400/x420_X4_400_rfnoc_image_core.yml | 155 +++++++++++++++++- 2 files changed, 284 insertions(+), 12 deletions(-) diff --git a/fpga/usrp3/top/x400/x420_CG_400_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_CG_400_rfnoc_image_core.yml index f93cfb5c4..34cf9b2fa 100644 --- a/fpga/usrp3/top/x400/x420_CG_400_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x420_CG_400_rfnoc_image_core.yml @@ -10,27 +10,152 @@ chdr_width: 512 # Bit width of the CHDR bus for this i device: 'x420' # USRP type image_core_name: 'usrp_x420_fpga_CG_400' # Name to use for the generated output files default_target: 'X420' # Default make target -# This image is identical to the 1000 MHz image, except for the RF bandwidth, -# which is achieved by adding resamplers with fixed factor of 3 in the RF data -# path inherit: - - 'x420_CG_1000_rfnoc_image_core.yml' + - 'yaml_include/x440_radio_base.yml' + - 'yaml_include/x4xx_cg_base.yml' parameters: + ENABLE_DRAM: True + NUM_DRAM_BANKS: 2 + NUM_DRAM_CHANS: 2 + DRAM_WIDTH: 512 RF_BW: 400 +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: False # Endpoint has no data interface + buff_size_bytes: 0 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size_bytes: 2097152 + ep2: + ctrl: False + data: True + buff_size_bytes: 2097152 + ep3: + ctrl: False + data: True + buff_size_bytes: 131072 + ep4: + ctrl: False + data: True + buff_size_bytes: 131072 + +# A table of which crossbar routes to include +# ------------------------------------------- +# Rows correspond to input ports and columns correspond to output ports. +# Entering a 1 includes and a 0 removes that route from the crossbar. +crossbar_routes: + # eth0 dma ep1 ep3 + # eth1 ep0 ep2 ep4 + - [ 1, 0, 0, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0) + - [ 0, 1, 0, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 1) + - [ 0, 0, 1, 1, 1, 1, 1, 1 ] # dma + - [ 1, 1, 1, 0, 0, 0, 0, 0 ] # ep0 (control only) + - [ 1, 1, 1, 0, 0, 0, 1, 1 ] # ep1 (radio0.0) + - [ 1, 1, 1, 0, 0, 0, 1, 1 ] # ep2 (radio1.0) + - [ 1, 1, 1, 0, 1, 1, 0, 0 ] # ep3 (replay0.0) + - [ 1, 1, 1, 0, 1, 1, 0, 0 ] # ep4 (replay1.0) + +# A list of all NoC blocks in design +# ---------------------------------- noc_blocks: + radio0: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 1 + EN_FIFO_OUT_REG: 1 + CTRL_FIFO_SIZE: 1024 + CTRL_OUT_FIFO_SIZE: 1024 + radio1: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 1 + EN_FIFO_OUT_REG: 1 + CTRL_FIFO_SIZE: 1024 + CTRL_OUT_FIFO_SIZE: 1024 duc0: + block_desc: 'duc.yml' parameters: - NIPC: 2 + NUM_PORTS: 1 duc1: + block_desc: 'duc.yml' parameters: - NIPC: 2 + NUM_PORTS: 1 ddc0: + block_desc: 'ddc.yml' parameters: - NIPC: 2 + NUM_PORTS: 1 ddc1: + block_desc: 'ddc.yml' parameters: - NIPC: 2 + NUM_PORTS: 1 + replay0: + block_desc: 'replay.yml' + parameters: + NUM_PORTS: 1 + MEM_DATA_W: 512 # has to match DRAM_WIDTH parameter above + MEM_ADDR_W: 32 + replay1: + block_desc: 'replay.yml' + parameters: + NUM_PORTS: 1 + MEM_DATA_W: 512 # has to match DRAM_WIDTH parameter above + MEM_ADDR_W: 32 + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # RF A:0 TX + - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_0 } + - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + # RF A:0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } + - { srcblk: ddc0, srcport: out_0, dstblk: ep1, dstport: in0 } + # RF B:0 TX + - { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 } + - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 } + # RF B:0 RX + - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 } + - { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 } + # Replay Connections + - { srcblk: ep3, srcport: out0, dstblk: replay0, dstport: in_0 } + - { srcblk: replay0, srcport: out_0, dstblk: ep3, dstport: in0 } + - { srcblk: ep4, srcport: out0, dstblk: replay1, dstport: in_0 } + - { srcblk: replay1, srcport: out_0, dstblk: ep4, dstport: in0 } + # + # BSP Connections + - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 } + - { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 } + # Front-Panel GPIO + - { srcblk: _device_, srcport: _none_, dstblk: _device_, dstport: gpio0 } + - { srcblk: _device_, srcport: _none_, dstblk: _device_, dstport: gpio1 } + # Other BSP connections are inherited from YAML include files + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce } + - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } + - { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem } + # Other clock domains are inherited from YAML include files + diff --git a/fpga/usrp3/top/x400/x420_X4_400_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_X4_400_rfnoc_image_core.yml index 3aed15da5..b95e2eb45 100644 --- a/fpga/usrp3/top/x400/x420_X4_400_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x420_X4_400_rfnoc_image_core.yml @@ -10,11 +10,158 @@ chdr_width: 256 # Bit width of the CHDR bus for this i device: 'x420' # USRP type image_core_name: 'usrp_x420_fpga_X4_400' # Name to use for the generated output files default_target: 'X420' # Default make target -# This image is identical to the 1000 MHz image, except for the RF bandwidth, -# which is achieved by adding resamplers with fixed factor of 3 in the RF data -# path inherit: - - 'x420_X4_1000_rfnoc_image_core.yml' + - 'yaml_include/x440_radio_base.yml' + - 'yaml_include/x4xx_x4_base.yml' parameters: RF_BW: 400 + ENABLE_DRAM: True + NUM_DRAM_BANKS: 2 + NUM_DRAM_CHANS: 2 + DRAM_WIDTH: 512 + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: False # Endpoint has no data interface + buff_size_bytes: 0 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size_bytes: 131072 + ep2: + ctrl: False + data: True + buff_size_bytes: 131072 + ep3: + ctrl: False + data: True + buff_size_bytes: 131072 + ep4: + ctrl: False + data: True + buff_size_bytes: 131072 + +# A table of which crossbar routes to include +# ------------------------------------------- +# Rows correspond to input ports and columns correspond to output ports. +# Entering a 1 includes and a 0 removes that route from the crossbar. +crossbar_routes: + # eth0 eth2 dma ep1 ep3 + # eth1 eth3 ep0 ep2 ep4 + - [ 1, 0, 0, 0, 0, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0) + - [ 0, 1, 0, 0, 0, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1) + - [ 0, 0, 1, 0, 0, 1, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2) + - [ 0, 0, 0, 1, 0, 1, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3) + - [ 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 ] # dma + - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 ] # ep0 (control only) + - [ 1, 1, 1, 1, 1, 0, 0, 0, 1, 1 ] # ep1 (radio0.0) + - [ 1, 1, 1, 1, 1, 0, 0, 0, 1, 1 ] # ep2 (radio1.0) + - [ 1, 1, 1, 1, 1, 0, 1, 1, 0, 0 ] # ep3 (replay0.0) + - [ 1, 1, 1, 1, 1, 0, 1, 1, 0, 0 ] # ep4 (replay1.0) + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + radio0: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 1 + EN_FIFO_OUT_REG: 1 + CTRL_FIFO_SIZE: 1024 + CTRL_OUT_FIFO_SIZE: 1024 + radio1: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 1 + EN_FIFO_OUT_REG: 1 + CTRL_FIFO_SIZE: 1024 + CTRL_OUT_FIFO_SIZE: 1024 + duc0: + block_desc: 'duc.yml' + parameters: + NUM_PORTS: 1 + NIPC: 4 + duc1: + block_desc: 'duc.yml' + parameters: + NUM_PORTS: 1 + NIPC: 4 + ddc0: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 1 + NIPC: 4 + ddc1: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 1 + NIPC: 4 + replay0: + block_desc: 'replay.yml' + parameters: + NUM_PORTS: 1 + MEM_DATA_W: 512 # has to match DRAM_WIDTH parameter above + MEM_ADDR_W: 32 + replay1: + block_desc: 'replay.yml' + parameters: + NUM_PORTS: 1 + MEM_DATA_W: 512 # has to match DRAM_WIDTH parameter above + MEM_ADDR_W: 32 + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +# +connections: + # RF A:0 TX + - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_0 } + - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + # RF A:0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } + - { srcblk: ddc0, srcport: out_0, dstblk: ep1, dstport: in0 } + # + # RF B:0 TX + - { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 } + - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 } + # RF B:0 RX + - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 } + - { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 } + # + # Replay Connections + - { srcblk: ep3, srcport: out0, dstblk: replay0, dstport: in_0 } + - { srcblk: replay0, srcport: out_0, dstblk: ep3, dstport: in0 } + - { srcblk: ep4, srcport: out0, dstblk: replay1, dstport: in_0 } + - { srcblk: replay1, srcport: out_0, dstblk: ep4, dstport: in0 } + # + # BSP Connections + - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 } + - { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 } + # Front-Panel GPIO + - { srcblk: _device_, srcport: _none_, dstblk: _device_, dstport: gpio0 } + - { srcblk: _device_, srcport: _none_, dstblk: _device_, dstport: gpio1 } + # Other BSP connections are inherited from YAML include files + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device_") +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce } + - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } + - { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem } + # Other clock domains are inherited from YAML include files