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fpga: ci: remove unused default values for x400 FPGA builds

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Max Köhler 2026-02-04 11:06:20 +01:00 committed by mkoop-ni
parent fa8b5bcdf4
commit 9a65a5d6e8
4 changed files with 30 additions and 236 deletions
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148
.ci/fpga/devices/job-build-fpga-x400.yml
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@ -37,142 +37,14 @@ parameters:
- name: fpga_imgs_source
type: string
default: 'Mono Pipeline'
# X410 FPGA targets to build(if triggered by changeset, packaging enabled)
- name: x410_full_targets_matrix
# X410 FPGA targets to build
- name: x410_targets_matrix
type: object
default:
X410_X4_100:
image_core: x410_X4_100_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_X4_100
target_name: X410
artifact_name: X410_X4_100
timeout: 720
attempt_timeout: 360
max_attempts: 2
X410_X4_200:
image_core: x410_X4_200_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_X4_200
target_name: X410
artifact_name: X410_X4_200
timeout: 720
attempt_timeout: 360
max_attempts: 2
X410_UC_200:
image_core: x410_UC_200_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_UC_200
target_name: X410
artifact_name: X410_UC_200
timeout: 720
attempt_timeout: 360
max_attempts: 2
X410_X4_400:
image_core: x410_X4_400_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_X4_400
target_name: X410
artifact_name: X410_X4_400
timeout: 720
attempt_timeout: 360
max_attempts: 2
X410_CG_400:
image_core: x410_CG_400_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_CG_400
target_name: X410
artifact_name: X410_CG_400
timeout: 720
attempt_timeout: 360
max_attempts: 2
- name: x410_reduced_targets_matrix
# X410 FPGA targets to build (if triggered by changeset, no packaging)
default: {}
# X440 FPGA targets to build
- name: x440_targets_matrix
type: object
default:
X410_X4_100:
image_core: x410_X4_100_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_X4_100
target_name: X410
artifact_name: X410_X4_100
timeout: 720
attempt_timeout: 360
max_attempts: 2
X410_X4_200:
image_core: x410_X4_200_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_X4_200
target_name: X410
artifact_name: X410_X4_200
timeout: 720
attempt_timeout: 360
max_attempts: 2
X410_X4_400:
image_core: x410_X4_400_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_X4_400
target_name: X410
artifact_name: X410_X4_400
timeout: 720
attempt_timeout: 360
max_attempts: 2
# X440 FPGA targets to build(if triggered by changeset, packaging enabled)
- name: x440_full_targets_matrix
type: object
default:
X440_CG_1600:
image_core: x440_CG_1600_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_CG_1600
target_name: X440
artifact_name: X440_CG_1600
timeout: 720
attempt_timeout: 360
max_attempts: 2
X440_CG_400:
image_core: x440_CG_400_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_CG_400
target_name: X440
artifact_name: X440_CG_400
timeout: 1080
attempt_timeout: 540 # successfull runs can take longer than default 6h
max_attempts: 2
X440_X4_1600:
image_core: x440_X4_1600_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_X4_1600
target_name: X440
artifact_name: X440_X4_1600
timeout: 720
attempt_timeout: 360
max_attempts: 2
X440_X4_400:
image_core: x440_X4_400_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_X4_400
target_name: X440
artifact_name: X440_X4_400
timeout: 1080
attempt_timeout: 540 # successfull runs can take longer than default 6h
max_attempts: 2
X440_X4_200:
image_core: x440_X4_200_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_X4_200
target_name: X440
artifact_name: X440_X4_200
timeout: 720
attempt_timeout: 360
max_attempts: 2
# X440 FPGA targets to build (if triggered by changeset, no packaging)
- name: x440_reduced_targets_matrix
type: object
default:
X440_CG_400:
image_core: x440_CG_400_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_CG_400
target_name: X440
artifact_name: X440_CG_400
timeout: 720
attempt_timeout: 360
max_attempts: 2
X440_X4_400:
image_core: x440_X4_400_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_X4_400
target_name: X440
artifact_name: X440_X4_400
timeout: 720
attempt_timeout: 360
max_attempts: 2
default: {}
- name: additional_setup_steps
type: stepList
default: []
@ -208,8 +80,8 @@ stages:
package_access: ${{ parameters.package_access }}
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
top_dir: uhddev/fpga/usrp3/top/x400
target_full_matrix: ${{ parameters.x410_full_targets_matrix }}
target_reduced_matrix: ${{ parameters.x410_reduced_targets_matrix }}
target_full_matrix: ${{ parameters.x410_targets_matrix }}
target_reduced_matrix: ${{ parameters.x410_targets_matrix }}
additional_setup_steps: ${{ parameters.additional_setup_steps }}
rfnoc_include_dir: ${{ parameters.rfnoc_include_dir }}
@ -236,8 +108,8 @@ stages:
package_access: ${{ parameters.package_access }}
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
top_dir: uhddev/fpga/usrp3/top/x400
target_full_matrix: ${{ parameters.x440_full_targets_matrix }}
target_reduced_matrix: ${{ parameters.x440_reduced_targets_matrix }}
target_full_matrix: ${{ parameters.x440_targets_matrix }}
target_reduced_matrix: ${{ parameters.x440_targets_matrix }}
additional_setup_steps: ${{ parameters.additional_setup_steps }}
rfnoc_include_dir: ${{ parameters.rfnoc_include_dir }}

8
.ci/fpga/templates/job-build-fpga-all.yml
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@ -60,12 +60,8 @@ stages:
publish_int_files: ${{ parameters.publish_int_files }}
package_and_publish_images: ${{ parameters.package_and_publish_images }}
package_access: ${{ parameters.package_access }}
${{ if ne(length(parameters.x410_targets_matrix), 0) }}:
x410_full_targets_matrix: ${{ parameters.x410_targets_matrix }}
x410_reduced_targets_matrix: ${{ parameters.x410_targets_matrix }}
${{ if ne(length(parameters.x440_targets_matrix), 0) }}:
x440_full_targets_matrix: ${{ parameters.x440_targets_matrix }}
x440_reduced_targets_matrix: ${{ parameters.x440_targets_matrix }}
x410_targets_matrix: ${{ parameters.x410_targets_matrix }}
x440_targets_matrix: ${{ parameters.x440_targets_matrix }}
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
additional_setup_steps: ${{ parameters.additional_setup_steps }}
rfnoc_include_dir: ${{ parameters.rfnoc_include_dir }}

18
.ci/templates/stages-uhd-pipeline.yml
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@ -98,6 +98,7 @@ parameters:
X410_X4_400:
image_core: x410_X4_400_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_X4_400
target_name: X410
artifact_name: X410_X4_400
timeout: 720
attempt_timeout: 360
@ -105,13 +106,23 @@ parameters:
X410_UC_200:
image_core: x410_UC_200_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_UC_200
target_name: X410
artifact_name: X410_UC_200
timeout: 720
attempt_timeout: 360
max_attempts: 2
X410_X4_100:
image_core: x410_X4_100_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_X4_100
target_name: X410
artifact_name: X410_X4_100
timeout: 720
attempt_timeout: 360
max_attempts: 2
X410_X4_200:
image_core: x410_X4_200_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_X4_200
target_name: X410
artifact_name: X410_X4_200
timeout: 720
attempt_timeout: 360
@ -119,6 +130,7 @@ parameters:
X410_CG_400:
image_core: x410_CG_400_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_CG_400
target_name: X410
artifact_name: X410_CG_400
timeout: 720
attempt_timeout: 360
@ -126,6 +138,7 @@ parameters:
X410_FFT_BLOCK_TEST:
image_core: ../../../../host/tests/rfnoc_block_tests_on_target/x410_fft_block_test.yml
image_core_name: usrp_x410_fpga_fft_block_test
target_name: X410
artifact_name: X410_FFT_BLOCK_TEST
timeout: 720
attempt_timeout: 360
@ -137,6 +150,7 @@ parameters:
X440_CG_1600:
image_core: x440_CG_1600_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_CG_1600
target_name: X440
artifact_name: X440_CG_1600
timeout: 720
attempt_timeout: 360
@ -144,6 +158,7 @@ parameters:
X440_CG_400:
image_core: x440_CG_400_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_CG_400
target_name: X440
artifact_name: X440_CG_400
timeout: 1080
attempt_timeout: 540 # successfull runs can take longer than default 6h
@ -151,6 +166,7 @@ parameters:
X440_X4_1600:
image_core: x440_X4_1600_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_X4_1600
target_name: X440
artifact_name: X440_X4_1600
timeout: 720
attempt_timeout: 360
@ -158,6 +174,7 @@ parameters:
X440_X4_400:
image_core: x440_X4_400_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_X4_400
target_name: X440
artifact_name: X440_X4_400
timeout: 1080
attempt_timeout: 540 # successfull runs can take longer than default 6h
@ -165,6 +182,7 @@ parameters:
X440_X4_200:
image_core: x440_X4_200_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_X4_200
target_name: X440
artifact_name: X440_X4_200
timeout: 720
attempt_timeout: 360

92
.ci/uhd-pipeline-pr.yml
View File

@ -131,96 +131,6 @@ parameters:
- 'files.ettus.com (Public)'
displayName: Published Package Access
default: 'Internal'
# Requested X410 targets
- name: x410_targets_matrix
type: object
displayName: X410 Targets
default:
X410_UC_200:
image_core: x410_UC_200_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_UC_200
target_name: X410
artifact_name: X410_UC_200
timeout: 720
attempt_timeout: 360
max_attempts: 2
X410_X4_100:
image_core: x410_X4_100_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_X4_100
target_name: X410
artifact_name: X410_X4_100
timeout: 720
attempt_timeout: 360
max_attempts: 2
X410_X4_200:
image_core: x410_X4_200_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_X4_200
target_name: X410
artifact_name: X410_X4_200
timeout: 720
attempt_timeout: 360
max_attempts: 2
X410_CG_400:
image_core: x410_CG_400_rfnoc_image_core.yml
image_core_name: usrp_x410_fpga_CG_400
target_name: X410
artifact_name: X410_CG_400
timeout: 720
attempt_timeout: 360
max_attempts: 2
X410_FFT_BLOCK_TEST:
image_core: ../../../../host/tests/rfnoc_block_tests_on_target/x410_fft_block_test.yml
image_core_name: usrp_x410_fpga_fft_block_test
target_name: X410
artifact_name: X410_FFT_BLOCK_TEST
timeout: 720
attempt_timeout: 360
max_attempts: 2
- name: x440_targets_matrix
type: object
displayName: X440 Targets
default:
X440_CG_1600:
image_core: x440_CG_1600_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_CG_1600
target_name: X440
artifact_name: X440_CG_1600
timeout: 720
attempt_timeout: 360
max_attempts: 2
X440_CG_400:
image_core: x440_CG_400_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_CG_400
target_name: X440
artifact_name: X440_CG_400
timeout: 1080
attempt_timeout: 540 # successfull runs can take longer than default 6h
max_attempts: 2
X440_X4_1600:
image_core: x440_X4_1600_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_X4_1600
target_name: X440
artifact_name: X440_X4_1600
timeout: 720
attempt_timeout: 360
max_attempts: 2
X440_X4_400:
image_core: x440_X4_400_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_X4_400
target_name: X440
artifact_name: X440_X4_400
timeout: 1080
attempt_timeout: 540 # successfull runs can take longer than default 6h
max_attempts: 2
X440_X4_200:
image_core: x440_X4_200_rfnoc_image_core.yml
image_core_name: usrp_x440_fpga_X4_200
target_name: X440
artifact_name: X440_X4_200
timeout: 720
attempt_timeout: 360
max_attempts: 2
trigger: none
@ -268,5 +178,3 @@ extends:
publish_int_files: true
package_and_publish_images: ${{ parameters.package_and_publish_images }}
package_access: ${{ parameters.package_access }}
x410_targets_matrix: ${{ parameters.x410_targets_matrix }}
x440_targets_matrix: ${{ parameters.x440_targets_matrix }}