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docs: Add timed complex gain to documentation

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Add a new section to the changelog regarding changed bitfile
behavior, specifically regarding the crossbar changes between
radio and replay block connections of the x440_X4_400 bitfile.

Change the standard bitfile description in manual to reflect
changes in x440_X4_400 bitfile behaviour changes. Add comment
to x440_X4_400 config regarding how to revert changes.
This commit is contained in:
Niels Garibaldi 2025-11-12 11:57:48 +01:00 committed by Jörg Hofrichter
parent 73022fb6d7
commit 956f3a7b1a
3 changed files with 83 additions and 16 deletions
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21
CHANGELOG
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@ -10,8 +10,21 @@ Change Log for Releases
- Add helper routines to up- and download data (reliably) from and to the
DRAM block
- X310: Allow daughterboards to set dboard clock rate
- RFNoC: Add names and descriptions for block's and module's YAML files, so
that other tools may read information about those in an automated fashion
- RFNoC:
- Added new optional feature to all Radio blocks - Timed complex gain:
- Allows specifying complex gain coefficients to be applied to all
TX and/or RX samples of a radio channel at the specified time.
- Enabled by default for all TX and RX channels of the radio blocks,
but can be disabled at FPGA build time via the`EN_COMP_GAIN_TX`
and `EN_COMP_GAIN_RX` parameters of the radio blocks.
- NOTE: For the x440_X4_400 default FPGA design provided with UHD,
enabling this feature for all 8 RX and TX channels necessitated
restricting the existing crossbar connections between the replay
blocks and the radio blocks. As a result, only blocks with the same
indicies can be connected (e.g. replay0<->radio0 and replay1<->radio1
only) when using this pre-built USRP FPGA image.
- Add names and descriptions for block's and module's YAML files, so
that other tools may read information about those in an automated fashion
* API Changes
- meta_range_t and uhd::dict can now be initialized from initializer lists
* Bug Fixes
@ -53,7 +66,7 @@ Change Log for Releases
a valid block YAML file, the tool will now automatically call `make-yaml` to
generate a new YAML file.
- Added support for processing multiple samples per cycle in FFT block.
- LabVIEW/USRP: New repository containing example applications which
- LabVIEW/USRP: New repository containing example applications which
demonstrate how to use NI LabVIEW with USRP devices via the UHD APIs.
(https://github.com/ni/labview-usrp-examples)
- Improved RFNoC OOT Block support:
@ -63,7 +76,7 @@ Change Log for Releases
to and from Aurora capable compute nodes like FPGA Coprocessors.
- Enhanced the UHD Windows installer to automatically install Windows
driver packages into the OS, eliminating this manual post-installation
step for B-Series USB devices.
step for B-Series USB devices.
* API Changes
- `uhd::math::gcd` and `uhd::math::lcm` are removed from the public
headers. Use `std::gcd` and `std::lcm` instead if C++17 is available,

47
fpga/usrp3/top/x400/x440_X4_400_rfnoc_image_core.yml
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@ -118,6 +118,53 @@ crossbar_routes:
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep14 (replay1.2)
- [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep15 (replay1.3)
# NOTE: The above Crossbar configuration was changed post UHD 4.9.0
# to accommodate the new complex gain feature in the Radio blocks.
# This configuration only allows connections between Radio and Replay
# blocks of the same index, e.g. Radio0<->Replay0 and Radio1<->Replay1
# respectively.
# All connections between Radio0<->Replay1 and Radio1<->Replay0
# have been removed. Please update your host applications accordingly
# to reflect these changes when upgrading from UHD 4.9.0 or earlier.
#
# To restore the behavior of UHD releases 4.9 and earlier, please follow
# these steps:
# - Uncomment the following crossbar_routes section and comment out the
# current crossbar_routes section above.
# - In the noc_blocks section below, disable the complex gain feature for
# both radio0 and radio1 blocks by adding the following entries to
# each radio block's parameters section:
# EN_COMP_GAIN_TX: 0
# EN_COMP_GAIN_RX: 0
# - Save the updated rfnoc_image_core YAML file and rebuild the FPGA image
# using the rfnoc_image_builder utility (Vivado required).
#
#
# crossbar_routes:
# # eth0 eth2 dma ep1 ep3 ep5 ep7 ep9 ep11 ep13 ep15
# # eth1 eth3 ep0 ep2 ep4 ep6 ep8 ep10 ep12 ep14
# - [ 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0)
# - [ 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1)
# - [ 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2)
# - [ 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3)
# - [ 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma
# - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep0 (radio0.0)
# - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep1 (radio0.1)
# - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep2 (radio0.2)
# - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep3 (radio0.3)
# - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep4 (radio1.0)
# - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep5 (radio1.1)
# - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep6 (radio1.2)
# - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep7 (radio1.3)
# - [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep8 (replay0.0)
# - [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep9 (replay0.1)
# - [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep10 (replay0.2)
# - [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep11 (replay0.3)
# - [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep12 (replay1.0)
# - [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep13 (replay1.1)
# - [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep14 (replay1.2)
# - [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep15 (replay1.3)
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:

31
host/docs/devices/usrp_x4xx.dox
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@ -572,21 +572,23 @@ indicates that each QSFP port has a single 100 GbE, respectively
As of UHD 4.5, the following USRP X410 images flavors are shipped with UHD:
| FPGA Image Flavor | Number of \n Channels | Bandwidth \n per Channel | QSFP28 Port 0 Interface | QSFP28 Port 1 Interface | DDC/DUC | DRAM |
|-------------------|-----------------------|--------------------------|-------------------------|-------------------------|---------|--------------------------|
| X4_200 | 4 (2 per ZBX) | 200 MHz | 4x 10 GbE (All Lanes) | Unused | Yes | Yes (4 GiB, 4-Ch Replay) |
| UC_200 | 4 (2 per ZBX) | 200 MHz | Unused | 100 GbE | Yes | Yes (4 GiB, 4-Ch Replay) |
| CG_400 | 4 (2 per ZBX) | 400 MHz | 100 GbE | 100 GbE | No | No |
| FPGA Image Flavor | Number of \n Channels | Bandwidth \n per Channel | QSFP28 Port 0 Interface | QSFP28 Port 1 Interface | DDC/DUC | DRAM |
|-------------------|-----------------------|--------------------------|-------------------------|-------------------------|---------|----------------------------|
| X4_200 | 4 (2 per ZBX) | 200 MHz | 4x 10 GbE (All Lanes) | Unused | Yes | Yes (4 GiB, 4-Ch Replay) |
| UC_200 | 4 (2 per ZBX) | 200 MHz | Unused | 100 GbE | Yes | Yes (4 GiB, 4-Ch Replay) |
| CG_400 | 4 (2 per ZBX) | 400 MHz | 100 GbE | 100 GbE | No | No |
As of UHD 4.6, the following USRP X440 images flavors are shipped with UHD:
| FPGA Image Flavor | Number of \n Channels | Bandwidth \n per Channel | QSFP28 Port 0 Interface | QSFP28 Port 1 Interface | DDC/DUC | DRAM |
|-------------------|-----------------------|--------------------------|-------------------------|-------------------------|---------|--------------------------|
| X4_200 | 8 (4 per FBX) | 200 MHz | 4x 10 GbE (All Lanes) | Unused | Yes | No |
| X4_400 | 8 (4 per FBX) | 400 MHz | 4x 10 GbE (All Lanes) | Unused | No | Yes (8 GiB, 8-Ch Replay) |
| CG_400 | 8 (4 per FBX) | 400 MHz | 100 GbE | 100 GbE | No | No |
| X4_1600 | 2 (1 per FBX) | 1600 MHz | 4x 10 GbE (All Lanes) | Unused | No | Yes (8 GiB, 2-Ch Replay) |
| CG_1600 | 2 (1 per FBX) | 1600 MHz | 100 GbE | 100 GbE | No | No |
| FPGA Image Flavor | Number of \n Channels | Bandwidth \n per Channel | QSFP28 Port 0 Interface | QSFP28 Port 1 Interface | DDC/DUC | DRAM |
|-------------------|-----------------------|--------------------------|-------------------------|-------------------------|---------|---------------------------|
| X4_200 | 8 (4 per FBX) | 200 MHz | 4x 10 GbE (All Lanes) | Unused | Yes | No |
| X4_400 | 8 (4 per FBX) | 400 MHz | 4x 10 GbE (All Lanes) | Unused | No | Yes (8 GiB, 8-Ch Replay*) |
| CG_400 | 8 (4 per FBX) | 400 MHz | 100 GbE | 100 GbE | No | No |
| X4_1600 | 2 (1 per FBX) | 1600 MHz | 4x 10 GbE (All Lanes) | Unused | No | Yes (8 GiB, 2-Ch Replay) |
| CG_1600 | 2 (1 per FBX) | 1600 MHz | 100 GbE | 100 GbE | No | No |
* (Implemented as two separate 4-Ch Replay blocks)
The following list shows some potential use-cases for different FPGA images:
@ -604,6 +606,11 @@ The following list shows some potential use-cases for different FPGA images:
DRAM using the RFNoC Record/Replay block. Up to 4 x 10 GbE connections may be
used to access the DRAM from an external host computer. Note that 10 GbE is
not fast enough for continuous full-rate streaming at this rate.
The replay feature is implemented as two, equally sized RFNoC Record/Replay
blocks. Record/Replay block 0 is connected to Radio block 0 (i.e., all RF
channels on daughterboard 0) and Record/Replay block 1 is connected to Radio
block 1. Cross-connections Record/Replay0 <-> Radio1 and Record/Replay1 <->
Radio0 are not supported by default.
(For USRP X410 this design is available as source, and not shipped as precompiled bitfile)
- `CG_1600` (USRP X440 only): Highest bandwidth streaming between the X440 and
an external host computer. Streaming requires one 100 GbE connections per