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fpga: b310: add CPLD jtag constraints
This commit is contained in:
Javier Valenzuela
Wade Fife
parent
556b378912
commit
8745af720e
@ -434,6 +434,88 @@ set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_
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set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_clocks clk_250mhz_x0y0]
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set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_clocks clk_250mhz_x0y0]
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set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_clocks jesd_ref_clk]
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set_clock_groups -asynchronous -group [get_clocks fpga_to_cpld_clk] -group [get_clocks jesd_ref_clk]
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#*******************************************************************************
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## CPLD JTAG Interface
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#
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# TCK frequency = bus_clk / (2*(prescalar+1))
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# prescalar used by utilities = 12 → TCK ≈ 5.76 MHz (period ≈ 173 ns)
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#
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# Protocol:
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# - TDI and TMS are launched on the falling edge of TCK (FSM HIGH→LOW transition)
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# and captured by the CPLD on the rising edge of TCK.
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# - TDO is launched by the CPLD on the falling edge of TCK and captured by the
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# FPGA bitq_fsm on the rising edge of TCK (FSM LOW→HIGH transition).
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# divide_by 26 matches prescalar=12
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create_generated_clock \
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-source [get_pins -hierarchical -filter {NAME =~ "*bus_clk_gen_i*CLKOUT0"}] \
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-name jtag_cpld_tck_clk_out \
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-divide_by 26 \
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[get_ports JTAG_CPLD_TCK]
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# CPLD JTAG timing parameters
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# Board trace delays: conservative estimate for PCB traces (in reality, these are short ~0.7-1 in)
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set jtag_cpld_tck_max_trace 1.0 ;# TCK board trace max delay (ns)
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set jtag_cpld_tck_min_trace 0.0 ;# TCK board trace min delay (ns)
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set jtag_cpld_data_max_trace 1.0 ;# TDI/TMS board trace max delay (ns)
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set jtag_cpld_data_min_trace 0.0 ;# TDI/TMS board trace min delay (ns)
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set jtag_cpld_tdo_max_trace 1.0 ;# TDO board trace max delay (ns)
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set jtag_cpld_tdo_min_trace 0.0 ;# TDO board trace min delay (ns)
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# CPLD JTAG device requirements: From MACHXO2 datasheet
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set jtag_cpld_tdi_setup 10.0 ;# CPLD JTAG TDI/TMS setup before TCK rising (ns)
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set jtag_cpld_tdi_hold 8.0 ;# CPLD JTAG TDI/TMS hold after TCK rising (ns)
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set jtag_cpld_tdo_max_clk_to_out 10.0 ;# CPLD JTAG TDO max clock-to-output after TCK falling (ns)
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set jtag_cpld_tdo_min_clk_to_out 0.0 ;# CPLD JTAG TDO min clock-to-output after TCK falling (ns)
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# -------------------------------------------------------
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# -- Constraint for CPLD JTAG TDI and TMS (outputs) --
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# -------------------------------------------------------
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set_output_delay -clock jtag_cpld_tck_clk_out \
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-max [expr {$jtag_cpld_tdi_setup + $jtag_cpld_data_max_trace - $jtag_cpld_tck_min_trace}] \
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[get_ports {JTAG_CPLD_TDI JTAG_CPLD_TMS}]
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set_output_delay -clock jtag_cpld_tck_clk_out \
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-min [expr {0 - $jtag_cpld_tck_max_trace - $jtag_cpld_tdi_hold + $jtag_cpld_data_min_trace}] \
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[get_ports {JTAG_CPLD_TDI JTAG_CPLD_TMS}]
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# -------------------------------------------------------
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# -- Multi-cycle path for CPLD JTAG TDI and TMS --
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# -------------------------------------------------------
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# TDI and TMS are launched on the falling edge of TCK (half period before the capture
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# rising edge). With divide_by=26, data is stable for 13 bus_clk cycles before capture.
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#
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# bus_clk __/--\__/--\__ ... __/--\__/--\__/--\__ ... __/--\__/--\__/--\__
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# TCK __/------------------------\________________________/-----------
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# | launch edge (falling TCK)
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# | | ... | | |
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# 0 1 ... 12 13* 14
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# Edge used for setup N = 13
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# | | ... | | | ... |
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# 25 24 ... 13 12 11 ... 0
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# (Setup -1) edge, in case
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# of no hold multi-cycle path
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# |
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# \____ Edge used for hold = 25
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set_multicycle_path -setup -start -to [get_ports {JTAG_CPLD_TDI JTAG_CPLD_TMS}] 13
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set_multicycle_path -hold -start -to [get_ports {JTAG_CPLD_TDI JTAG_CPLD_TMS}] 25
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# -------------------------------------------------------
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# -- Constraint for CPLD JTAG TDO (input) --
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# -------------------------------------------------------
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# TDO is launched by the CPLD on the falling edge of TCK and captured at the
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# next rising edge of TCK inside the bitq_fsm. Waveform is similar to TDI/TMS.
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set_input_delay -clock_fall -clock jtag_cpld_tck_clk_out \
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-max [expr {$jtag_cpld_tck_max_trace + $jtag_cpld_tdo_max_clk_to_out + $jtag_cpld_tdo_max_trace}] \
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[get_ports JTAG_CPLD_TDO]
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set_input_delay -clock_fall -clock jtag_cpld_tck_clk_out \
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-min [expr {$jtag_cpld_tck_min_trace + $jtag_cpld_tdo_min_clk_to_out + $jtag_cpld_tdo_min_trace}] \
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[get_ports JTAG_CPLD_TDO]
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# TDO multi-cycle path: same half-period relationship as TDI/TMS.
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set_multicycle_path -setup -end -from [get_ports JTAG_CPLD_TDO] 13
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set_multicycle_path -hold -end -from [get_ports JTAG_CPLD_TDO] 25
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#*******************************************************************************
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#*******************************************************************************
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## Authentication chip interface timing
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## Authentication chip interface timing
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@ -448,28 +530,24 @@ set_max_delay -datapath_only -from [get_ports AUTH_SDA] -to [all_registers -edge
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# #*******************************************************************************
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# #*******************************************************************************
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# ## ADRV9032 SPI Interface
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# ## ADRV9032 SPI Interface
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set adrv_spi_clk_register [get_pins {b310_core_i/ctrlport_spi_adrv_i/axis_spi_i/sclk_reg/Q}]
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create_generated_clock -source [get_clocks radio_clk] \
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-name adrv_spi_clk $adrv_spi_clk_register \
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-divide_by 30
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create_generated_clock \
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create_generated_clock \
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-source $adrv_spi_clk_register \
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-source [get_pins -hierarchical -filter {NAME =~ "*radio_clk_gen_i/*/CLKOUT0"}] \
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-name adrv_spi_clk_out [get_ports {ADRV_SPI_CLK}]
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-name adrv_spi_clk_out \
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-divide_by 30 \
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[get_ports {ADRV_SPI_CLK}]
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# DIO trace length is 2138.37 nils, which is roughly 0.36 ns. The main source for propagation delay
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# DIO trace length is 2138.37 nils, which is roughly 0.36 ns. The main source for propagation delay
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# in this trace comes from filtering circuitry on the ADRV side slowing down rise times. The measured
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# in this trace comes from filtering circuitry on the ADRV side slowing down rise times. The measured
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# delay is ~32ns. The constraint below is a conservative number to ensure timing closure.
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# delay is ~32ns. The constraint below is a conservative number to ensure timing closure.
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set adrv_dio_max_trace_delay 75.0
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set adrv_dio_max_trace_delay 50.0
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set adrv_dio_min_trace_delay 0.0
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set adrv_dio_min_trace_delay 0.0
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# DO and CS has similar considerations as DIO, with both having a measured delay of ~45ns.
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# DO and CS has similar considerations as DIO, with both having a measured delay of ~45ns.
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set adrv_do_max_trace_delay 75.0
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set adrv_do_max_trace_delay 50.0
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set adrv_do_min_trace_delay 0.0
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set adrv_do_min_trace_delay 0.0
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set adrv_cs_max_trace_delay 75.0
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set adrv_cs_max_trace_delay 50.0
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set adrv_cs_min_trace_delay 0.0
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set adrv_cs_min_trace_delay 0.0
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# And yet again, we conservatively constraint the delay of the SPI clock, measured at ~25ns.
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# And yet again, we conservatively constraint the delay of the SPI clock, measured at ~25ns.
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set adrv_clk_max_trace_delay 50.0
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set adrv_clk_max_trace_delay 35.0
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set adrv_clk_min_trace_delay 0.0
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set adrv_clk_min_trace_delay 0.0
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# Values from the ADRV9032 datasheet, in ns
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# Values from the ADRV9032 datasheet, in ns
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@ -510,10 +588,10 @@ set_output_delay -clock adrv_spi_clk_out \
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# 0 1 2 ... 14 15* 16
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# 0 1 2 ... 14 15* 16
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# Edge used for
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# Edge used for
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# setup analysis N = 15
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# setup analysis N = 15
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# | | | | | | | ... | |
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# | | | | | | | ... |
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# 29 28 27 ... 16 15 14 13 ... 1 0
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# 29 28 27 ... 15 14 13 12 ... 0
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# (Setup -1) edge, in case
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# (Setup -1) edge, in case
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# of no hold multi-cycle path
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# of no hold multi-cycle path
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# |
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# |
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# \____ Edge used for hold = 29
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# \____ Edge used for hold = 29
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#
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#
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@ -544,11 +622,11 @@ set_multicycle_path -hold -end -from [get_ports {ADRV_SPI_DO}] 29
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# we will use conservative numbers that far exceed its trace delay to ensure timing closure
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# we will use conservative numbers that far exceed its trace delay to ensure timing closure
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# for all devices on this interface.
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# for all devices on this interface.
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set clocking_output_max_trace_delay 50.0
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set clocking_output_max_trace_delay 10.0
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set clocking_output_min_trace_delay 0.0
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set clocking_output_min_trace_delay 0.0
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set clocking_miso_max_trace_delay 50.0
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set clocking_miso_max_trace_delay 10.0
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set clocking_miso_min_trace_delay 0.0
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set clocking_miso_min_trace_delay 0.0
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set clocking_sclk_max_trace_delay 50.0
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set clocking_sclk_max_trace_delay 10.0
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set clocking_sclk_min_trace_delay 0.0
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set clocking_sclk_min_trace_delay 0.0
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# Values from datasheets, in ns
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# Values from datasheets, in ns
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@ -560,16 +638,13 @@ set clock_spi_hold 0.0
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set clock_spi_max_tco 60.0
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set clock_spi_max_tco 60.0
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set clock_spi_min_tco 0.0
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set clock_spi_min_tco 0.0
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set clocking_sclk_register [get_pins {b310_core_i/clocking_spi_engine/sclk_reg_reg/Q}]
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# SPI divider uses default value of 30.
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# SPI divider uses default value of 30.
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create_generated_clock -source [get_clocks bus_clk] \
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-name clocking_spi_clk $clocking_sclk_register \
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-divide_by 30
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create_generated_clock \
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create_generated_clock \
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-source $clocking_sclk_register \
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-source [get_pins -hierarchical -filter {NAME =~ "*bus_clk_gen_i*CLKOUT0"}] \
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-name clocking_spi_clk_out [get_ports {LMK32_SCLK LMK053_SCLK DAC_SCLK}]
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-name clocking_spi_clk_out \
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-divide_by 30 \
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[get_ports {LMK32_SCLK LMK053_SCLK DAC_SCLK}]
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# ---------------------------------------------
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# ---------------------------------------------
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@ -600,10 +675,10 @@ set_output_delay -clock clocking_spi_clk_out \
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# 0 1 2 ... 14 15* 16
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# 0 1 2 ... 14 15* 16
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# Edge used for
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# Edge used for
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# setup analysis N = 15
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# setup analysis N = 15
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# | | | | | | | ... | |
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# | | | | | | | ... |
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# 29 28 27 ... 16 15 14 13 ... 1 0
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# 29 28 27 ... 15 14 13 12 ... 0
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# (Setup -1) edge, in case
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# (Setup -1) edge, in case
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# of no hold multi-cycle path
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# of no hold multi-cycle path
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# |
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# |
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# \____ Edge used for hold = 29
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# \____ Edge used for hold = 29
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#
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#
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