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fpga: lib: fixup i2c non-blocking assignments

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Javier Valenzuela 2026-09-03 22:05:14 -05:00 committed by Frank Dietze
parent 04a7f8c6bf
commit 7351887ab5
1 changed files with 7 additions and 7 deletions
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14
fpga/usrp3/lib/control/ctrlport_to_wb_i2c.v
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@ -110,19 +110,19 @@ module ctrlport_to_wb_i2c #(
end end
case (s_ctrlport_req_addr) case (s_ctrlport_req_addr)
BASE_ADDRESS + WB_PRER_LO * REG_STRIDE_SIZE: begin BASE_ADDRESS + WB_PRER_LO * REG_STRIDE_SIZE: begin
wb_adr_i = WB_PRER_LO; wb_adr_i <= WB_PRER_LO;
end end
BASE_ADDRESS + WB_PRER_HI * REG_STRIDE_SIZE: begin BASE_ADDRESS + WB_PRER_HI * REG_STRIDE_SIZE: begin
wb_adr_i = WB_PRER_HI; wb_adr_i <= WB_PRER_HI;
end end
BASE_ADDRESS + WB_CTR * REG_STRIDE_SIZE: begin BASE_ADDRESS + WB_CTR * REG_STRIDE_SIZE: begin
wb_adr_i = WB_CTR; wb_adr_i <= WB_CTR;
end end
BASE_ADDRESS + WB_TXR * REG_STRIDE_SIZE: begin BASE_ADDRESS + WB_TXR * REG_STRIDE_SIZE: begin
wb_adr_i = WB_TXR; wb_adr_i <= WB_TXR;
end end
BASE_ADDRESS + WB_CR * REG_STRIDE_SIZE: begin BASE_ADDRESS + WB_CR * REG_STRIDE_SIZE: begin
wb_adr_i = WB_CR; wb_adr_i <= WB_CR;
end end
endcase endcase
@ -146,10 +146,10 @@ module ctrlport_to_wb_i2c #(
wb_adr_i <= WB_CTR; wb_adr_i <= WB_CTR;
end end
BASE_ADDRESS + WB_RXR * REG_STRIDE_SIZE: begin BASE_ADDRESS + WB_RXR * REG_STRIDE_SIZE: begin
wb_adr_i = WB_RXR; wb_adr_i <= WB_RXR;
end end
BASE_ADDRESS + WB_SR * REG_STRIDE_SIZE: begin BASE_ADDRESS + WB_SR * REG_STRIDE_SIZE: begin
wb_adr_i = WB_SR; wb_adr_i <= WB_SR;
end end
// Respond with 0 // Respond with 0
default: begin default: begin