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B100: enable_gpif(0) disables FIFO output clock on FX2. this prevents the "stuffing zeroes" problem and improves transport reliability.

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This commit is contained in:
Nick Foster 2012-03-16 11:26:34 -07:00
parent f91e247da2
commit 63991f7922
2 changed files with 4 additions and 4 deletions
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4
firmware/fx2/b100/usrp_main.c
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@ -87,9 +87,9 @@ static void clear_fifo(int ep) {
void enable_xfers(int enable) {
if(enable) {
IFCONFIG |= bmIFSLAVE;
IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmIFSLAVE;
} else {
IFCONFIG &= ~bmIFSLAVE;
IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFSLAVE;
}
set_led_0(enable);
}

4
host/lib/usrp/b100/b100_impl.cpp
View File

@ -182,12 +182,11 @@ b100_impl::b100_impl(const device_addr_t &device_addr){
//-- setup clock after making fx2 and before loading fpga --//
_clock_ctrl = b100_clock_ctrl::make(_fx2_ctrl, device_addr.cast<double>("master_clock_rate", B100_DEFAULT_TICK_RATE));
//load FPGA image, gpif is disabled while loading
//load FPGA image, slave xfers are disabled while loading
this->enable_gpif(false);
_fx2_ctrl->usrp_load_fpga(b100_fpga_image);
_fx2_ctrl->usrp_fpga_reset(false); //active low reset
_fx2_ctrl->usrp_fpga_reset(true);
this->enable_gpif(true);
//create the control transport
device_addr_t ctrl_xport_args;
@ -203,6 +202,7 @@ b100_impl::b100_impl(const device_addr_t &device_addr){
ctrl_xport_args
);
while (_ctrl_transport->get_recv_buff(0.0)){} //flush ctrl xport
this->enable_gpif(true);
////////////////////////////////////////////////////////////////////
// Initialize FPGA wishbone communication