diff --git a/fpga/usrp3/lib/dsp/cic_comb_filter.sv b/fpga/usrp3/lib/dsp/cic_comb_filter.sv
index 5c5a2fa3d..b63d44521 100644
--- a/fpga/usrp3/lib/dsp/cic_comb_filter.sv
+++ b/fpga/usrp3/lib/dsp/cic_comb_filter.sv
@@ -56,13 +56,17 @@
 //    SPC           : Number of samples processed per clock cycle. Must be a
 //                    power of 2 and at least 1.
 //
+//    FIFO_SIZE     : Log2 of the depth of the output buffer FIFO. Set to 0 for
+//                    a single-stage flop.
+//
 
 
 `default_nettype none
 
 module cic_comb_filter #(
   parameter int ACCUM_W        = 96,
-  parameter int SPC            = 4
+  parameter int SPC            = 4,
+  parameter int FIFO_SIZE      = 0
 ) (
   input wire              clk,
   input wire              rst,
@@ -178,14 +182,15 @@ module cic_comb_filter #(
   //---------------------------------------------------------------------------
   // Output FIFO (single stage)
   //
-  // Breaks the combinational path from data_out.tready to data_in.tready.
+  // Optionally breaks the combinational path from data_out.tready to
+  // data_in.tready.
   //---------------------------------------------------------------------------
 
   logic [SPC*ACCUM_W:0] fifo_out_tdata;
 
   axi_fifo #(
     .WIDTH(SPC * ACCUM_W + 1),
-    .SIZE (1)
+    .SIZE (FIFO_SIZE)
   ) output_buffer (
     .clk     (clk),
     .reset   (rst),
diff --git a/fpga/usrp3/lib/dsp/cic_filter_decim.sv b/fpga/usrp3/lib/dsp/cic_filter_decim.sv
index 2748a4337..07599f634 100644
--- a/fpga/usrp3/lib/dsp/cic_filter_decim.sv
+++ b/fpga/usrp3/lib/dsp/cic_filter_decim.sv
@@ -202,8 +202,9 @@ module cic_filter_decim #(
   //---------------------------------------------------------------------------
   for (genvar stage = 0; stage < ORDER; stage++) begin : gen_combs
     cic_comb_filter #(
-      .ACCUM_W (ACCUM_W),
-      .SPC     (SPC)
+      .ACCUM_W  (ACCUM_W),
+      .SPC      (SPC),
+      .FIFO_SIZE((stage == ORDER-1)? 1 : 0)
     ) cic_comb_filter_i (
       .clk     (clk),
       .rst     (rst),
diff --git a/fpga/usrp3/lib/dsp/cic_filter_interp.sv b/fpga/usrp3/lib/dsp/cic_filter_interp.sv
index 07757094a..0094d42ef 100644
--- a/fpga/usrp3/lib/dsp/cic_filter_interp.sv
+++ b/fpga/usrp3/lib/dsp/cic_filter_interp.sv
@@ -175,8 +175,9 @@ module cic_filter_interp #(
   //---------------------------------------------------------------------------
   for (genvar stage = 0; stage < ORDER; stage++) begin : gen_combs
     cic_comb_filter #(
-      .ACCUM_W (ACCUM_W),
-      .SPC     (SPC)
+      .ACCUM_W  (ACCUM_W),
+      .SPC      (SPC),
+      .FIFO_SIZE((stage == ORDER-1)? 1 : 0)
     ) cic_comb_filter_i (
       .clk     (clk),
       .rst     (rst),