diff --git a/fpga/usrp3/top/b300/b310_fifo_rfnoc_image_core.yml b/fpga/usrp3/top/b300/b310_fifo_rfnoc_image_core.yml index 26ecbcbe3..1852003ed 100644 --- a/fpga/usrp3/top/b300/b310_fifo_rfnoc_image_core.yml +++ b/fpga/usrp3/top/b300/b310_fifo_rfnoc_image_core.yml @@ -71,7 +71,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/b300/b310_replay_rfnoc_image_core.yml b/fpga/usrp3/top/b300/b310_replay_rfnoc_image_core.yml index b90f27b7a..d53df3866 100644 --- a/fpga/usrp3/top/b300/b310_replay_rfnoc_image_core.yml +++ b/fpga/usrp3/top/b300/b310_replay_rfnoc_image_core.yml @@ -85,7 +85,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/b300/yaml_include/b310_radio_base.yml b/fpga/usrp3/top/b300/yaml_include/b310_radio_base.yml index 18ee27e4f..dba50f93b 100644 --- a/fpga/usrp3/top/b300/yaml_include/b310_radio_base.yml +++ b/fpga/usrp3/top/b300/yaml_include/b310_radio_base.yml @@ -60,7 +60,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.yml b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.yml index e9a4f838b..0e1458524 100644 --- a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.yml +++ b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.yml @@ -59,7 +59,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml b/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml index 30800fabd..21b073447 100644 --- a/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml +++ b/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml @@ -97,7 +97,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.yml index 4e5ad5fc4..b0e4aa752 100644 --- a/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.yml +++ b/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.yml @@ -95,7 +95,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml index 52ff63371..970de789d 100644 --- a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml +++ b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml @@ -93,7 +93,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.yml index 4b0d9aab5..d586621e5 100644 --- a/fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.yml +++ b/fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.yml @@ -120,7 +120,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml index 06eec5c6f..64b12c12c 100644 --- a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml +++ b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml @@ -145,7 +145,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.yml index 5aef0b813..a53c5f520 100644 --- a/fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.yml +++ b/fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.yml @@ -106,7 +106,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml index f2603f170..b446dd61a 100644 --- a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml +++ b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml @@ -111,7 +111,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x300/x300_HG_rfnoc_image_core.yml b/fpga/usrp3/top/x300/x300_HG_rfnoc_image_core.yml index 9d378d63e..55d84b89f 100644 --- a/fpga/usrp3/top/x300/x300_HG_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x300/x300_HG_rfnoc_image_core.yml @@ -65,7 +65,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x300/x300_XG_rfnoc_image_core.yml b/fpga/usrp3/top/x300/x300_XG_rfnoc_image_core.yml index 975e40774..4dec32055 100644 --- a/fpga/usrp3/top/x300/x300_XG_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x300/x300_XG_rfnoc_image_core.yml @@ -65,7 +65,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x300/x310_HG_rfnoc_image_core.yml b/fpga/usrp3/top/x300/x310_HG_rfnoc_image_core.yml index c2a142863..d8971f674 100644 --- a/fpga/usrp3/top/x300/x310_HG_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x300/x310_HG_rfnoc_image_core.yml @@ -65,7 +65,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x300/x310_XG_rfnoc_image_core.yml b/fpga/usrp3/top/x300/x310_XG_rfnoc_image_core.yml index c7ff1ae18..a3dda03ee 100644 --- a/fpga/usrp3/top/x300/x310_XG_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x300/x310_XG_rfnoc_image_core.yml @@ -65,7 +65,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x300/yaml_include/x3xx_radio_base.yml b/fpga/usrp3/top/x300/yaml_include/x3xx_radio_base.yml index 0cda4ada9..650c7f845 100644 --- a/fpga/usrp3/top/x300/yaml_include/x3xx_radio_base.yml +++ b/fpga/usrp3/top/x300/yaml_include/x3xx_radio_base.yml @@ -44,7 +44,7 @@ noc_blocks: parameters: NUM_PORTS: 2 EN_COMP_GAIN_TX: 1 - EN_COMP_GAIN_RX: 1 + EN_COMP_GAIN_RX: 1 duc1: block_desc: 'duc.yml' parameters: @@ -105,7 +105,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/x410_UC_200_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x410_UC_200_rfnoc_image_core.yml index a5b57548f..cd4e5e668 100644 --- a/fpga/usrp3/top/x400/x410_UC_200_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x410_UC_200_rfnoc_image_core.yml @@ -163,7 +163,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/x410_X4_200_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x410_X4_200_rfnoc_image_core.yml index a1330b6bc..77c316b89 100644 --- a/fpga/usrp3/top/x400/x410_X4_200_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x410_X4_200_rfnoc_image_core.yml @@ -144,7 +144,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/x410_XG_200_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x410_XG_200_rfnoc_image_core.yml index b4dc32a60..a2a0aa841 100644 --- a/fpga/usrp3/top/x400/x410_XG_200_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x410_XG_200_rfnoc_image_core.yml @@ -144,7 +144,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/x420_CG_1000_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_CG_1000_rfnoc_image_core.yml index c7a627db5..af465fdb5 100644 --- a/fpga/usrp3/top/x400/x420_CG_1000_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x420_CG_1000_rfnoc_image_core.yml @@ -147,7 +147,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml index 288fa8e80..3f06b48fc 100644 --- a/fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x420_CG_1000_woDDC_rfnoc_image_core.yml @@ -123,7 +123,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/x420_CG_400_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_CG_400_rfnoc_image_core.yml index 34cf9b2fa..348dc2d2d 100644 --- a/fpga/usrp3/top/x400/x420_CG_400_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x420_CG_400_rfnoc_image_core.yml @@ -144,7 +144,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/x420_X4_1000_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_X4_1000_rfnoc_image_core.yml index 150585ccd..447038753 100644 --- a/fpga/usrp3/top/x400/x420_X4_1000_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x420_X4_1000_rfnoc_image_core.yml @@ -152,7 +152,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/x420_X4_200_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x420_X4_200_rfnoc_image_core.yml index 2cce41703..b072188f7 100644 --- a/fpga/usrp3/top/x400/x420_X4_200_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x420_X4_200_rfnoc_image_core.yml @@ -147,7 +147,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/x440_X1_200_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x440_X1_200_rfnoc_image_core.yml index 1b4b9d265..4fe385417 100644 --- a/fpga/usrp3/top/x400/x440_X1_200_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x440_X1_200_rfnoc_image_core.yml @@ -240,7 +240,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/x440_X4_1600_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x440_X4_1600_rfnoc_image_core.yml index 065c454b5..a32b30f13 100644 --- a/fpga/usrp3/top/x400/x440_X4_1600_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x440_X4_1600_rfnoc_image_core.yml @@ -137,7 +137,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/x440_X4_200_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x440_X4_200_rfnoc_image_core.yml index fed07ff59..fcbb22e4e 100644 --- a/fpga/usrp3/top/x400/x440_X4_200_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x440_X4_200_rfnoc_image_core.yml @@ -173,7 +173,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/x440_X4_400_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x440_X4_400_rfnoc_image_core.yml index 1eb048324..f94a60a80 100644 --- a/fpga/usrp3/top/x400/x440_X4_400_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x440_X4_400_rfnoc_image_core.yml @@ -124,7 +124,7 @@ crossbar_routes: # This configuration only allows connections between Radio and Replay # blocks of the same index, e.g. Radio0<->Replay0 and Radio1<->Replay1 # respectively. -# All connections between Radio0<->Replay1 and Radio1<->Replay0 +# All connections between Radio0<->Replay1 and Radio1<->Replay0 # have been removed. Please update your host applications accordingly # to reflect these changes when upgrading from UHD 4.9.0 or earlier. # @@ -139,7 +139,7 @@ crossbar_routes: # EN_COMP_GAIN_RX: 0 # - Save the updated rfnoc_image_core YAML file and rebuild the FPGA image # using the rfnoc_image_builder utility (Vivado required). -# +# # # crossbar_routes: # # eth0 eth2 dma ep1 ep3 ep5 ep7 ep9 ep11 ep13 ep15 @@ -260,7 +260,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/yaml_include/x410_radio_base.yml b/fpga/usrp3/top/x400/yaml_include/x410_radio_base.yml index 81d41a810..a1f143fe7 100644 --- a/fpga/usrp3/top/x400/yaml_include/x410_radio_base.yml +++ b/fpga/usrp3/top/x400/yaml_include/x410_radio_base.yml @@ -52,7 +52,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/fpga/usrp3/top/x400/yaml_include/x440_radio_base.yml b/fpga/usrp3/top/x400/yaml_include/x440_radio_base.yml index 6c891c8f1..af8f71055 100644 --- a/fpga/usrp3/top/x400/yaml_include/x440_radio_base.yml +++ b/fpga/usrp3/top/x400/yaml_include/x440_radio_base.yml @@ -50,7 +50,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/host/examples/rfnoc-gain/icores/x310_rfnoc_image_core.yml b/host/examples/rfnoc-gain/icores/x310_rfnoc_image_core.yml index c3c5f7bd2..39457cc60 100644 --- a/host/examples/rfnoc-gain/icores/x310_rfnoc_image_core.yml +++ b/host/examples/rfnoc-gain/icores/x310_rfnoc_image_core.yml @@ -111,7 +111,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/host/examples/rfnoc-gain/icores/x410_XG_200_rfnoc_image_core.yml b/host/examples/rfnoc-gain/icores/x410_XG_200_rfnoc_image_core.yml index 503726adb..04275fcd0 100644 --- a/host/examples/rfnoc-gain/icores/x410_XG_200_rfnoc_image_core.yml +++ b/host/examples/rfnoc-gain/icores/x410_XG_200_rfnoc_image_core.yml @@ -153,7 +153,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect diff --git a/host/tests/rfnoc_block_tests_on_target/x410_fft_block_test.yml b/host/tests/rfnoc_block_tests_on_target/x410_fft_block_test.yml index e04b722bb..914ff53c8 100644 --- a/host/tests/rfnoc_block_tests_on_target/x410_fft_block_test.yml +++ b/host/tests/rfnoc_block_tests_on_target/x410_fft_block_test.yml @@ -115,7 +115,7 @@ connections: # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device"_) +# - srcblk = Source block to connect (Always "_device_") # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect