ci: add rfnoc complex gain tests

.ci/templates/steps-download-fpga-artifact.yml

@@ -38,14 +38,13 @@ steps:
     echo FPGA_ARTIFACT_DIR=$ARTIFACT_DIR
     echo '##vso[task.setvariable variable=FPGA_BITFILE_NAME]'$BITFILE_NAME
     echo FPGA_BITFILE_NAME=$BITFILE_NAME
-  name: fpga_artifact
-  displayName: "FPGA artifact: Set variables"
+  displayName: "${{ parameters.dutFPGA }}: FPGA artifact: Set variables"
 
 - script: |
     rm -rfv "$FPGA_ARTIFACT_DIR"
-  displayName: "FPGA artifact: Cleanup"
+  displayName: "${{ parameters.dutFPGA }}: FPGA artifact: Cleanup"
 
 - download: ${{ parameters.fpgaArtifactSource }}
   artifact: $(FPGA_ARTIFACT_NAME)
-  displayName: "FPGA artifact: Download"
+  displayName: "${{ parameters.dutFPGA }}: FPGA artifact: Download"
   condition: and(succeeded(), eq('${{ parameters.fpga_imgs_source }}', 'Pipeline'))

.ci/templates/steps-rfnoc-block-test.yml

@@ -11,6 +11,15 @@ parameters:
 - name: fpga_imgs_source
   type: string
   default: Pipeline
+- name: dutFPGA
+  type: string
+  default: 'fft_block_test'
+- name: resultFileNameBase
+  type: string
+  default: 'fft_block_test'
+- name: testSelector
+  type: string
+  default: 'test_fft_block*.py'
 
 steps:
   - script: |
@@ -22,27 +31,27 @@ steps:
       echo UHDDEV_LIB_DIR=$UHD_INSTALL_PATH/lib
       echo '##vso[task.setvariable variable=UHDDEV_PYTHONPATH]'$PYTHONPATH
       echo UHDDEV_PYTHONPATH=$PYTHONPATH
-    displayName: "rfnoc block test: set variables"
+    displayName: "${{ parameters.resultFileNameBase }}: Set Variables"
     env:
       UHD_INSTALL_PATH: ${{ parameters.uhdInstallPath }}
 
   - template: steps-download-fpga-artifact.yml
     parameters:
       dutType: ${{ parameters.dutType }}
-      dutFPGA: fft_block_test
+      dutFPGA: ${{ parameters.dutFPGA }}
       fpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
       fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
 
   - script: |
       uhd_image_loader --args ${{ parameters.uhdArgs }} --fpga=$FPGA_ARTIFACT_DIR/$FPGA_BITFILE_NAME.bit
-    displayName: "rfnoc block test: Load FPGA on USRP"
+    displayName: "${{ parameters.resultFileNameBase }}: Load FPGA on USRP"
     env:
       PATH: /usr/bin/:$(UHDDEV_BIN_DIR)
       LD_LIBRARY_PATH: $(UHDDEV_LIB_DIR)
 
   - script: |
       uhd_usrp_probe --args ${{ parameters.uhdArgs }}
-    displayName: "rfnoc block test: Probe USRP"
+    displayName: "${{ parameters.resultFileNameBase }}: Probe USRP"
     env:
       PATH: /usr/bin/:$(UHDDEV_BIN_DIR)
       LD_LIBRARY_PATH: $(UHDDEV_LIB_DIR)
@@ -52,8 +61,8 @@ steps:
       source rfnoc-block-test-venv/bin/activate
       TEST_DIR=$(Build.SourcesDirectory)/uhddev/host/tests/rfnoc_block_tests_on_target
       pip install -r $TEST_DIR/requirements.txt
-      pytest --args ${{ parameters.uhdArgs }} $TEST_DIR/test_fft_block*.py -vv --junitxml=$(Common.TestResultsDirectory)/rfnoc-block-test.xml
-    displayName: "rfnoc block test: Run test"
+      pytest --args ${{ parameters.uhdArgs }} $TEST_DIR/${{ parameters.testSelector }} -vv --junitxml=$(Common.TestResultsDirectory)/${{ parameters.resultFileNameBase }}.xml
+    displayName: "${{ parameters.resultFileNameBase }}: Run test"
     env:
       PATH: /usr/bin/:$(UHDDEV_BIN_DIR)
       LD_LIBRARY_PATH: $(UHDDEV_LIB_DIR)
@@ -62,8 +71,8 @@ steps:
   - task: PublishTestResults@2
     inputs:
       testResultsFormat: 'JUnit'
-      testResultsFiles: '$(Common.TestResultsDirectory)/rfnoc-block-test.xml'
-      testRunTitle: rfnoc-module-test-${{ parameters.dutType }}
+      testResultsFiles: '$(Common.TestResultsDirectory)/${{ parameters.resultFileNameBase }}.xml'
+      testRunTitle: ${{ parameters.resultFileNameBase }}-${{ parameters.dutType }}
       mergeTestResults: true
       failTaskOnFailedTests: true
-    displayName: "rfnoc block test: Upload Test Result"
+    displayName: "${{ parameters.resultFileNameBase }}: Upload Test Result"

.ci/templates/tests/templates/job-uhd-x4xx-hardware-tests.yml

@@ -405,6 +405,20 @@ jobs:
         uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
         fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
         uhdArgs: type=$(dutType),addr=$(USRP_EMB_TARGET_IP)
+        dutFPGA: 'fft_block_test'
+        resultFileNameBase: 'fft_block_test'
+        testSelector: 'test_fft_block_*.py'
+
+    - template: ../../steps-rfnoc-block-test.yml
+      parameters:
+        dutType: $(pytestDUT)
+        uhdInstallPath: $(uhd_artifact_directory)/uhddev-$(testOS)-${{ parameters.toolset }}/uhddev/build-installed
+        uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
+        fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
+        uhdArgs: type=$(dutType),addr=$(USRP_EMB_TARGET_IP)
+        dutFPGA: 'X4_200'
+        resultFileNameBase: 'complex_gain_block_test'
+        testSelector: 'test_radio_control_complex_gain.py'
 
   # Run the mender tests last because they
   # modify the flashed image on the device