diff --git a/fpga/usrp3/lib/ip/Makefile.inc b/fpga/usrp3/lib/ip/Makefile.inc index 0996cac94..3af7b499a 100644 --- a/fpga/usrp3/lib/ip/Makefile.inc +++ b/fpga/usrp3/lib/ip/Makefile.inc @@ -22,6 +22,11 @@ include $(LIB_IP_DIR)/divide_int32/Makefile.inc include $(LIB_IP_DIR)/divide_uint32/Makefile.inc include $(LIB_IP_DIR)/divide_int16_int32/Makefile.inc include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc +include $(LIB_IP_DIR)/xfft_4k_16b/Makefile.inc +include $(LIB_IP_DIR)/xfft_8k_16b/Makefile.inc +include $(LIB_IP_DIR)/xfft_16k_16b/Makefile.inc +include $(LIB_IP_DIR)/xfft_32k_16b/Makefile.inc +include $(LIB_IP_DIR)/xfft_64k_16b/Makefile.inc LIB_IP_XCI_SRCS = \ $(LIB_IP_AXI_FFT_SRCS) \ @@ -41,7 +46,14 @@ $(LIB_IP_DIVIDE_INT24_SRCS) \ $(LIB_IP_DIVIDE_INT32_SRCS) \ $(LIB_IP_DIVIDE_UINT32_SRCS) \ $(LIB_IP_DIVIDE_INT16_INT32_SRCS) \ -$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) +$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \ +$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \ +$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \ +$(LIB_IP_XFFT_4K_16B_SRCS) \ +$(LIB_IP_XFFT_8K_16B_SRCS) \ +$(LIB_IP_XFFT_16K_16B_SRCS) \ +$(LIB_IP_XFFT_32K_16B_SRCS) \ +$(LIB_IP_XFFT_64K_16B_SRCS) \ LIB_IP_SYNTH_OUTPUTS = \ $(LIB_IP_AXI_FFT_OUTS) \ @@ -62,7 +74,12 @@ $(LIB_IP_DIVIDE_INT32_OUTS) \ $(LIB_IP_DIVIDE_UINT32_OUTS) \ $(LIB_IP_DIVIDE_INT16_INT32_OUTS) \ $(LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS) \ -$(LIB_IP_DDS_SIN_COS_LUT_ONLY_OUTS) +$(LIB_IP_DDS_SIN_COS_LUT_ONLY_OUTS) \ +$(LIB_IP_XFFT_4K_16B_OUTS) \ +$(LIB_IP_XFFT_8K_16B_OUTS) \ +$(LIB_IP_XFFT_16K_16B_OUTS) \ +$(LIB_IP_XFFT_32K_16B_OUTS) \ +$(LIB_IP_XFFT_64K_16B_OUTS) \ lib_ip: $(LIB_IP_SYNTH_OUTPUTS) diff --git a/fpga/usrp3/lib/ip/xfft_16k_16b/Makefile.inc b/fpga/usrp3/lib/ip/xfft_16k_16b/Makefile.inc new file mode 100644 index 000000000..1cc6b5d0e --- /dev/null +++ b/fpga/usrp3/lib/ip/xfft_16k_16b/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2024 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +LIB_IP_XFFT_16K_16B_SRCS = $(IP_BUILD_DIR)/xfft_16k_16b/xfft_16k_16b.xci + +LIB_IP_XFFT_16K_16B_OUTS = $(addprefix $(IP_BUILD_DIR)/xfft_16k_16b/, \ +xfft_16k_16b.xci.out \ +synth/xfft_16k_16b.vhd \ +) + +$(LIB_IP_XFFT_16K_16B_SRCS) $(LIB_IP_XFFT_16K_16B_OUTS) : $(LIB_IP_DIR)/xfft_16k_16b/xfft_16k_16b.xci + $(call BUILD_VIVADO_IP,xfft_16k_16b,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/lib/ip/xfft_16k_16b/xfft_16k_16b.xci b/fpga/usrp3/lib/ip/xfft_16k_16b/xfft_16k_16b.xci new file mode 100644 index 000000000..6d3aa1d96 --- /dev/null +++ b/fpga/usrp3/lib/ip/xfft_16k_16b/xfft_16k_16b.xci @@ -0,0 +1,242 @@ + + + xilinx.com + xci + unknown + 1.0 + + + xfft_16k_16b + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 24 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.0 + 5 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + 3 + 1 + 7 + 1 + 2 + 1 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 16 + 32 + 24 + 8 + 14 + 0 + 16 + xczu28dr-ffvg1517-1-e + 1 + 40 + 32 + 1 + 1 + 24 + 0 + 0 + zynquplus + xfft_16k_16b + false + true + use_xtremedsp_slices + 1 + use_mults_performance + true + fixed_point + pipelined_streaming_io + 16 + block_ram + false + block_ram + block_ram + 7 + natural_order + true + 24 + convergent_rounding + true + scaled + 250 + 123 + nonrealtime + 16384 + true + zynquplusRFSOC + + + xczu28dr + ffvg1517 + VERILOG + + MIXED + -1 + + E + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/lib/ip/xfft_32k_16b/Makefile.inc b/fpga/usrp3/lib/ip/xfft_32k_16b/Makefile.inc new file mode 100644 index 000000000..274849932 --- /dev/null +++ b/fpga/usrp3/lib/ip/xfft_32k_16b/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2024 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +LIB_IP_XFFT_32K_16B_SRCS = $(IP_BUILD_DIR)/xfft_32k_16b/xfft_32k_16b.xci + +LIB_IP_XFFT_32K_16B_OUTS = $(addprefix $(IP_BUILD_DIR)/xfft_32k_16b/, \ +xfft_32k_16b.xci.out \ +synth/xfft_32k_16b.vhd \ +) + +$(LIB_IP_XFFT_32K_16B_SRCS) $(LIB_IP_XFFT_32K_16B_OUTS) : $(LIB_IP_DIR)/xfft_32k_16b/xfft_32k_16b.xci + $(call BUILD_VIVADO_IP,xfft_32k_16b,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/lib/ip/xfft_32k_16b/xfft_32k_16b.xci b/fpga/usrp3/lib/ip/xfft_32k_16b/xfft_32k_16b.xci new file mode 100644 index 000000000..17a028c59 --- /dev/null +++ b/fpga/usrp3/lib/ip/xfft_32k_16b/xfft_32k_16b.xci @@ -0,0 +1,242 @@ + + + xilinx.com + xci + unknown + 1.0 + + + xfft_32k_16b + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 24 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.0 + 6 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + 3 + 1 + 8 + 1 + 2 + 1 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 16 + 32 + 24 + 8 + 15 + 0 + 16 + xczu28dr-ffvg1517-1-e + 1 + 48 + 32 + 1 + 1 + 24 + 0 + 0 + zynquplus + xfft_32k_16b + false + true + use_xtremedsp_slices + 1 + use_mults_performance + true + fixed_point + pipelined_streaming_io + 16 + block_ram + false + block_ram + block_ram + 8 + natural_order + true + 24 + convergent_rounding + true + scaled + 250 + 123 + nonrealtime + 32768 + true + zynquplusRFSOC + + + xczu28dr + ffvg1517 + VERILOG + + MIXED + -1 + + E + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2021.1_AR76780 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/lib/ip/xfft_4k_16b/Makefile.inc b/fpga/usrp3/lib/ip/xfft_4k_16b/Makefile.inc new file mode 100644 index 000000000..fd8cd3148 --- /dev/null +++ b/fpga/usrp3/lib/ip/xfft_4k_16b/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2024 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +LIB_IP_XFFT_4K_16B_SRCS = $(IP_BUILD_DIR)/xfft_4k_16b/xfft_4k_16b.xci + +LIB_IP_XFFT_4K_16B_OUTS = $(addprefix $(IP_BUILD_DIR)/xfft_4k_16b/, \ +xfft_4k_16b.xci.out \ +synth/xfft_4k_16b.vhd \ +) + +$(LIB_IP_XFFT_4K_16B_SRCS) $(LIB_IP_XFFT_4K_16B_OUTS) : $(LIB_IP_DIR)/xfft_4k_16b/xfft_4k_16b.xci + $(call BUILD_VIVADO_IP,xfft_4k_16b,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/lib/ip/xfft_4k_16b/xfft_4k_16b.xci b/fpga/usrp3/lib/ip/xfft_4k_16b/xfft_4k_16b.xci new file mode 100644 index 000000000..15cac57ec --- /dev/null +++ b/fpga/usrp3/lib/ip/xfft_4k_16b/xfft_4k_16b.xci @@ -0,0 +1,242 @@ + + + xilinx.com + xci + unknown + 1.0 + + + xfft_4k_16b + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 24 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.0 + 5 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + 3 + 1 + 5 + 1 + 2 + 1 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 16 + 32 + 24 + 8 + 12 + 0 + 16 + xczu28dr-ffvg1517-1-e + 1 + 40 + 32 + 1 + 1 + 24 + 0 + 0 + zynquplus + xfft_4k_16b + false + true + use_xtremedsp_slices + 1 + use_mults_performance + true + fixed_point + pipelined_streaming_io + 16 + block_ram + false + block_ram + block_ram + 5 + natural_order + true + 24 + convergent_rounding + true + scaled + 250 + 123 + nonrealtime + 4096 + true + zynquplusRFSOC + + + xczu28dr + ffvg1517 + VERILOG + + MIXED + -1 + + E + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2021.1_AR76780 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/lib/ip/xfft_64k_16b/Makefile.inc b/fpga/usrp3/lib/ip/xfft_64k_16b/Makefile.inc new file mode 100644 index 000000000..6af24c3bf --- /dev/null +++ b/fpga/usrp3/lib/ip/xfft_64k_16b/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2024 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +LIB_IP_XFFT_64K_16B_SRCS = $(IP_BUILD_DIR)/xfft_64k_16b/xfft_64k_16b.xci + +LIB_IP_XFFT_64K_16B_OUTS = $(addprefix $(IP_BUILD_DIR)/xfft_64k_16b/, \ +xfft_64k_16b.xci.out \ +synth/xfft_64k_16b.vhd \ +) + +$(LIB_IP_XFFT_64K_16B_SRCS) $(LIB_IP_XFFT_64K_16B_OUTS) : $(LIB_IP_DIR)/xfft_64k_16b/xfft_64k_16b.xci + $(call BUILD_VIVADO_IP,xfft_64k_16b,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/lib/ip/xfft_64k_16b/xfft_64k_16b.xci b/fpga/usrp3/lib/ip/xfft_64k_16b/xfft_64k_16b.xci new file mode 100644 index 000000000..93c4dbd2c --- /dev/null +++ b/fpga/usrp3/lib/ip/xfft_64k_16b/xfft_64k_16b.xci @@ -0,0 +1,242 @@ + + + xilinx.com + xci + unknown + 1.0 + + + xfft_64k_16b + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 24 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.0 + 6 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + 3 + 1 + 9 + 1 + 2 + 1 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 16 + 32 + 24 + 8 + 16 + 0 + 16 + xczu28dr-ffvg1517-1-e + 1 + 48 + 32 + 1 + 1 + 24 + 0 + 0 + zynquplus + xfft_64k_16b + false + true + use_xtremedsp_slices + 1 + use_mults_performance + true + fixed_point + pipelined_streaming_io + 16 + block_ram + false + block_ram + block_ram + 9 + natural_order + true + 24 + convergent_rounding + true + scaled + 250 + 123 + nonrealtime + 65536 + true + zynquplusRFSOC + + + xczu28dr + ffvg1517 + VERILOG + + MIXED + -1 + + E + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/lib/ip/xfft_8k_16b/Makefile.inc b/fpga/usrp3/lib/ip/xfft_8k_16b/Makefile.inc new file mode 100644 index 000000000..5e30db5d6 --- /dev/null +++ b/fpga/usrp3/lib/ip/xfft_8k_16b/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2024 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +LIB_IP_XFFT_8K_16B_SRCS = $(IP_BUILD_DIR)/xfft_8k_16b/xfft_8k_16b.xci + +LIB_IP_XFFT_8K_16B_OUTS = $(addprefix $(IP_BUILD_DIR)/xfft_8k_16b/, \ +xfft_8k_16b.xci.out \ +synth/xfft_8k_16b.vhd \ +) + +$(LIB_IP_XFFT_8K_16B_SRCS) $(LIB_IP_XFFT_8K_16B_OUTS) : $(LIB_IP_DIR)/xfft_8k_16b/xfft_8k_16b.xci + $(call BUILD_VIVADO_IP,xfft_8k_16b,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/lib/ip/xfft_8k_16b/xfft_8k_16b.xci b/fpga/usrp3/lib/ip/xfft_8k_16b/xfft_8k_16b.xci new file mode 100644 index 000000000..9ddf83ff5 --- /dev/null +++ b/fpga/usrp3/lib/ip/xfft_8k_16b/xfft_8k_16b.xci @@ -0,0 +1,242 @@ + + + xilinx.com + xci + unknown + 1.0 + + + xfft_8k_16b + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 24 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.0 + 5 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + 3 + 1 + 6 + 1 + 2 + 1 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 16 + 32 + 24 + 8 + 13 + 0 + 16 + xczu28dr-ffvg1517-1-e + 1 + 40 + 32 + 1 + 1 + 24 + 0 + 0 + zynquplus + xfft_8k_16b + false + true + use_xtremedsp_slices + 1 + use_mults_performance + true + fixed_point + pipelined_streaming_io + 16 + block_ram + false + block_ram + block_ram + 6 + natural_order + true + 24 + convergent_rounding + true + scaled + 250 + 123 + nonrealtime + 8192 + true + zynquplusRFSOC + + + xczu28dr + ffvg1517 + VERILOG + + MIXED + -1 + + E + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2021.1_AR76780 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +