From 29c459f1b3aa9dc8acbc00d3f8995b83dd4166ff Mon Sep 17 00:00:00 2001 From: Lars Amsel Date: Wed, 19 Aug 2026 16:56:24 +0200 Subject: [PATCH] fpga: enable clock watch circuit on X440 images Enable clock watch circuit for images with 200 and 400MHz bandwidth as well. With this we also move from watch the rfdc_clk to watch the radio_clk. This makes is easier to calculate the max clock rate for all flavours of images. --- .../usrp3/top/x400/x440_CG_400_rfnoc_image_core.yml | 1 + .../usrp3/top/x400/x440_X4_200_rfnoc_image_core.yml | 1 + .../usrp3/top/x400/x440_X4_400_rfnoc_image_core.yml | 1 + fpga/usrp3/top/x400/x4xx.sv | 13 +++++++------ 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/fpga/usrp3/top/x400/x440_CG_400_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x440_CG_400_rfnoc_image_core.yml index 8e757efcc..50897e129 100644 --- a/fpga/usrp3/top/x400/x440_CG_400_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x440_CG_400_rfnoc_image_core.yml @@ -20,6 +20,7 @@ parameters: NUM_DRAM_BANKS: 0 NUM_DRAM_CHANS: 0 DRAM_WIDTH: 128 + ENABLE_CLOCK_WD: True # Enable 1GS/s limit for shipping bitfiles # A list of all stream endpoints in design # ---------------------------------------- diff --git a/fpga/usrp3/top/x400/x440_X4_200_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x440_X4_200_rfnoc_image_core.yml index db495a8f8..fed07ff59 100644 --- a/fpga/usrp3/top/x400/x440_X4_200_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x440_X4_200_rfnoc_image_core.yml @@ -21,6 +21,7 @@ parameters: NUM_DRAM_CHANS: 0 DRAM_WIDTH: 64 USE_FABRIC_RESAMPLERS: True + ENABLE_CLOCK_WD: True # Enable 1GS/s limit for shipping bitfiles # A list of all stream endpoints in design # ---------------------------------------- diff --git a/fpga/usrp3/top/x400/x440_X4_400_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x440_X4_400_rfnoc_image_core.yml index 14ca92297..1eb048324 100644 --- a/fpga/usrp3/top/x400/x440_X4_400_rfnoc_image_core.yml +++ b/fpga/usrp3/top/x400/x440_X4_400_rfnoc_image_core.yml @@ -20,6 +20,7 @@ parameters: NUM_DRAM_BANKS: 2 NUM_DRAM_CHANS: 8 DRAM_WIDTH: 128 + ENABLE_CLOCK_WD: True # Enable 1GS/s limit for shipping bitfiles # A list of all stream endpoints in design # ---------------------------------------- diff --git a/fpga/usrp3/top/x400/x4xx.sv b/fpga/usrp3/top/x400/x4xx.sv index bff9a8593..481b2aa31 100644 --- a/fpga/usrp3/top/x400/x4xx.sv +++ b/fpga/usrp3/top/x400/x4xx.sv @@ -624,10 +624,11 @@ module x4xx ( `endif if (`ENABLE_CLOCK_WD) begin : gen_clock_wd - // Mode-dependent max RFDC clock rate (in Hz) - // Maps sample rates to approximate rfdc_clk frequencies - // 125 MHz is the max rate for the RFDC interface clocks - localparam int MAX_RFDC_CLK_RATE = 1_000_000_000 / RFDC_SPC; + // Mode-dependent max radio clock rate (in Hz) + // Maps sample rates to approximate radio_clk frequencies + // 1 GHz is the max sample rate for the radio interface. + // Devide by radio samples per cycle to get the max radio clock rate. + localparam int MAX_RADIO_CLK_RATE = 1_000_000_000 / RADIO_SPC; wire mgt_refclk_i; wire mgt_refclk_fabric; @@ -667,13 +668,13 @@ module x4xx ( for (genvar db_i = 0; db_i < NUM_DBOARDS; db_i = db_i + 1) begin : gen_clocking_watchdog clocking_watchdog #( - .MAX_CLOCK_RATE(MAX_RFDC_CLK_RATE), + .MAX_CLOCK_RATE(MAX_RADIO_CLK_RATE), .MONITOR_CLK_FREQ(100_000_000) // mgt_refclk_fabric is 100 MHz ) rfdc_clocking_watchdog_i ( .monitor_clk (mgt_refclk_fabric), .rst (mgt_refclk_fabric_rst), .clock_locked (data_clock_locked), - .watched_clk (rfdc_clk[db_i]), + .watched_clk (radio_clk[db_i]), .clock_fault (rfdc_clk_fault[db_i]) ); end