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B200: Restore asynchronous reset of AD936x.

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This commit is contained in:
michael-west 2018-10-12 17:34:06 -07:00 committed by Brent Stapleton
parent b7b6af7521
commit 20f061689c
4 changed files with 20 additions and 9 deletions
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2
fpga-src

@ -1 +1 @@
Subproject commit 340bb076520b49f422af69a16bb02260edff5839
Subproject commit 0ac3353f8e2b8224368d34fd63f547e9a231c38e

11
host/lib/usrp/b200/b200_impl.cpp
View File

@ -585,6 +585,7 @@ b200_impl::b200_impl(const uhd::device_addr_t& device_addr, usb_device_handle::s
// Init codec - turns on clocks
////////////////////////////////////////////////////////////////////
UHD_LOGGER_INFO("B200") << "Initialize CODEC control..." ;
reset_codec();
ad9361_params::sptr client_settings;
if (_product == B200MINI or _product == B205MINI) {
client_settings = boost::make_shared<b2xxmini_ad9361_client_t>();
@ -1228,6 +1229,14 @@ void b200_impl::update_bandsel(const std::string& which, double freq)
update_gpio_state();
}
void b200_impl::reset_codec()
{
_gpio_state.codec_arst = 1;
update_gpio_state();
_gpio_state.codec_arst = 0;
update_gpio_state();
}
void b200_impl::update_gpio_state(void)
{
const uint32_t misc_word = 0
@ -1237,7 +1246,7 @@ void b200_impl::update_gpio_state(void)
| (_gpio_state.rx_bandsel_a << 5)
| (_gpio_state.rx_bandsel_b << 4)
| (_gpio_state.rx_bandsel_c << 3)
// Bit 2 currently not used.
| (_gpio_state.codec_arst << 2)
| (_gpio_state.mimo << 1)
| (_gpio_state.ref_sel << 0)
;

8
host/lib/usrp/b200/b200_impl.hpp
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@ -41,8 +41,8 @@
static const uint8_t B200_FW_COMPAT_NUM_MAJOR = 8;
static const uint8_t B200_FW_COMPAT_NUM_MINOR = 0;
static const uint16_t B200_FPGA_COMPAT_NUM = 15;
static const uint16_t B205_FPGA_COMPAT_NUM = 6;
static const uint16_t B200_FPGA_COMPAT_NUM = 16;
static const uint16_t B205_FPGA_COMPAT_NUM = 7;
static const double B200_BUS_CLOCK_RATE = 100e6;
static const uint32_t B200_GPSDO_ST_NONE = 0x83;
static const size_t B200_MAX_RATE_USB2 = 53248000; // bytes/s
@ -175,6 +175,7 @@ private:
void sync_times(void);
void update_clock_source(const std::string &);
void update_bandsel(const std::string& which, double freq);
void reset_codec(void);
void update_antenna_sel(const size_t which, const std::string &ant);
uhd::sensor_value_t get_ref_locked(void);
uhd::sensor_value_t get_fe_pll_locked(const bool is_tx);
@ -211,7 +212,7 @@ private:
void handle_overflow(const size_t radio_index);
struct gpio_state {
uint32_t tx_bandsel_a, tx_bandsel_b, rx_bandsel_a, rx_bandsel_b, rx_bandsel_c, mimo, ref_sel, swap_atr;
uint32_t tx_bandsel_a, tx_bandsel_b, rx_bandsel_a, rx_bandsel_b, rx_bandsel_c, codec_arst, mimo, ref_sel, swap_atr;
gpio_state() {
tx_bandsel_a = 0;
@ -219,6 +220,7 @@ private:
rx_bandsel_a = 0;
rx_bandsel_b = 0;
rx_bandsel_c = 0;
codec_arst = 0;
mimo = 0;
ref_sel = 0;
swap_atr = 0;

8
images/manifest.txt
View File

@ -24,10 +24,10 @@ n3xx_common_mender_default meta-ettus-v3.13.0.0 n3xx/meta-ettus-v3.13.0.0/
n3xx_common_sdimg_default meta-ettus-v3.13.0.0 n3xx/meta-ettus-v3.13.0.0/n3xx_common_sdimg_default-v3.13.0.0.zip 0
# B200-Series
b2xx_b200_fpga_default fpga-63e630a b2xx/fpga-63e630a/b2xx_b200_fpga_default-g63e630a.zip c42f010a90c9a184a2bf8ab7182dcbcc50598a259f06f9b5fda92023dc6cfed8
b2xx_b200mini_fpga_default fpga-63e630a b2xx/fpga-63e630a/b2xx_b200mini_fpga_default-g63e630a.zip 75ae4b16d8dc12ab8b38e7f380cb94e81c6065031aefd2e72972f65ec8c23842
b2xx_b210_fpga_default fpga-63e630a b2xx/fpga-63e630a/b2xx_b210_fpga_default-g63e630a.zip de7464dac5a1cd5be38811f3ec8239410ff5d9d2a8d199039e09de3c423bc63d
b2xx_b205mini_fpga_default fpga-63e630a b2xx/fpga-63e630a/b2xx_b205mini_fpga_default-g63e630a.zip d852c4f0038e6b12fed19303c7baabfd8785271aa00b327c80d22a39835661fa
b2xx_b200_fpga_default fpga-0ac3353f b2xx/fpga-0ac3353f/b2xx_b200_fpga_default-g0ac3353f.zip 762d71da3e29073955b8eb7e7dc87af8efef9f0d9162cd11d127308bec96741a
b2xx_b200mini_fpga_default fpga-0ac3353f b2xx/fpga-0ac3353f/b2xx_b200mini_fpga_default-g0ac3353f.zip 0a61b1caa9672b86a243f660b4fe51b40d1e99ba7e0713c353b4040544903c1a
b2xx_b210_fpga_default fpga-0ac3353f b2xx/fpga-0ac3353f/b2xx_b210_fpga_default-g0ac3353f.zip 5f056d4dc4deaa5021ca26bef9224e2b2dd7d0774429c33f4606dc7fe9607735
b2xx_b205mini_fpga_default fpga-0ac3353f b2xx/fpga-0ac3353f/b2xx_b205mini_fpga_default-g0ac3353f.zip f1db44f781de96190a78447e1779be27baa343a37a84f548d7d49dafaf1edf08
b2xx_common_fw_default uhd-455a288 b2xx/uhd-455a288/b2xx_common_fw_default-g455a288.zip ac53d8bf9cda7508cb3ee09d190de08495ba9e519279e77f9927eccc953144f6
# USRP2 Devices