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examples: Make IQ order clear in gain RFNoC block

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Wade Fife 2021-10-27 10:56:45 -05:00 committed by Aaron Rossetto
parent 4360e86945
commit 16b6c757fe
1 changed files with 25 additions and 16 deletions
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41
host/examples/rfnoc-example/fpga/rfnoc_block_gain/rfnoc_block_gain.v
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@ -1,5 +1,5 @@
//
// Copyright 2019 Ettus Research, A National Instruments Brand
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@ -32,7 +32,7 @@ module rfnoc_block_gain #(
parameter CHDR_W = 64,
parameter [5:0] MTU = 10,
parameter IP_OPTION = "HDL_IP"
)(
) (
// RFNoC Framework Clocks and Resets
input wire rfnoc_chdr_clk,
input wire rfnoc_ctrl_clk,
@ -234,7 +234,7 @@ module rfnoc_block_gain #(
localparam REG_GAIN_DEFAULT = 1; // Default gain value
reg [15:0] reg_gain = REG_GAIN_DEFAULT;
always @(posedge ctrlport_clk) begin
if (ctrlport_rst) begin
reg_gain = REG_GAIN_DEFAULT;
@ -267,20 +267,25 @@ module rfnoc_block_gain #(
//---------------------------------------------------------------------------
// Signal Processing
//---------------------------------------------------------------------------
//
// Multiply each complex sample by a real-valued gain. The RFNoC signals
// m_in_payload_* and m_out_payload_* expect the data with the real/I
// component on the upper bits [31:16] and the imaginary/Q component on the
// lower bits [15:0].
//
// We only input the real-valued gain (reg_gain) when we have payload data to
// go in (m_in_payload_*). That way the current gain value always applies to
// the current sample. This assumes that the tready of both inputs have
// identical behavior.
//
//---------------------------------------------------------------------------
wire [63:0] mult_tdata; // Multiply results in 32-bit I and 32-bit Q (sc32)
// Multiply result. I/real in [63:32], Q/imaginary in [31:0] (sc32).
wire [63:0] mult_tdata;
wire mult_tlast;
wire mult_tvalid;
wire mult_tready;
// Multiply each complex sample by a real-valued gain. Only input the gain
// when we have payload data to go in (m_in_payload_tdata). That way the
// current gain value always applies to the current sample. This assumes that
// the tready of both inputs have identical behavior.
//
// Note that we receive the data with I on bits [31:16] and Q on bits [15:0],
// but the I/Q order does not matter to our complex multiplier.
generate
// Use a generate statement to choose which IP to use for the multiply.
// These all do the same thing and we only have multiple options to show
@ -344,6 +349,9 @@ module rfnoc_block_gain #(
// Use the out-of-tree "cmplx_mul" IP, which is a Xilinx Complex
// Multiplier LogiCORE IP located in the IP directory of this example.
// This IP expects real/I in the lower bits and imaginary/Q in the upper
// bits, so we swap I and Q on the input and output to match RFNoC.
//
// This IP has a 33-bit output, but because it's AXI-Stream, each
// component is placed in a 5-byte word. Since our gain is real only,
// we'll never need all 33-bits.
@ -352,11 +360,12 @@ module rfnoc_block_gain #(
cmplx_mul cmplx_mul_i (
.aclk (axis_data_clk),
.aresetn (~axis_data_rst),
.s_axis_a_tdata ({16'd0, reg_gain}),
.s_axis_a_tdata ({16'd0, reg_gain}), // Real gain
.s_axis_a_tlast (m_in_payload_tlast),
.s_axis_a_tvalid (m_in_payload_tvalid),
.s_axis_a_tready (),
.s_axis_b_tdata (m_in_payload_tdata),
.s_axis_b_tdata ({m_in_payload_tdata[15:0], // Imaginary
m_in_payload_tdata[31:16]}), // Real
.s_axis_b_tlast (m_in_payload_tlast),
.s_axis_b_tvalid (m_in_payload_tvalid),
.s_axis_b_tready (m_in_payload_tready),
@ -366,8 +375,8 @@ module rfnoc_block_gain #(
.m_axis_dout_tready (mult_tready)
);
assign mult_tdata[31: 0] = m_axis_dout_tdata[31: 0];
assign mult_tdata[63:32] = m_axis_dout_tdata[71:40];
assign mult_tdata[63:32] = m_axis_dout_tdata[31: 0]; // Real
assign mult_tdata[31: 0] = m_axis_dout_tdata[71:40]; // Imaginary
end
endgenerate