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b200: Removed all AD9361 related firmware

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- FX3 does not respond to AD9361 firmware transaction VREQs
- FX3 does not respond to AD9361 SPI transaction VREQs
- Deleted all AD9361 firmware files
- Bumped FW compat to 6
This commit is contained in:
Ashish Chaudhari 2014-08-12 11:19:22 -07:00
parent 96d1d58673
commit 145f1d7cf7
16 changed files with 7 additions and 2832 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
firmware/README.md
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@ -18,7 +18,7 @@ __Build Instructions:__
## fx3/ ## fx3/
__Description:__ This is the firmware for the FX3 USB PHY, and the AD9361 RFIC. __Description:__ This is the firmware for the FX3 USB PHY.
__Devices:__ USRP B200 and USRP B210 __Devices:__ USRP B200 and USRP B210

7
firmware/fx3/README.md
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@ -9,10 +9,8 @@ show you how to build our firmware source
**A brief "Theory of Operations":** **A brief "Theory of Operations":**
The host sends commands to the FX3, our USB3 PHY, which has an on-board ARM The host sends commands to the FX3, our USB3 PHY, which has an on-board ARM
which runs the FX3 firmware code (hex file). That code translates commands into which runs the FX3 firmware code (hex file). That code is responsible for
SPI commands to/from the AD9361. The SPI lines run through the FPGA (bin or bit managing the transport from the host to the FPGA by configuring IO and DMA.
file), where they are level-translated, and then head to the AD9361. Note that
the FPGA takes no action on these SPI lines. They are passive pass-throughs.
## Setting up the Cypress SDK ## Setting up the Cypress SDK
@ -46,7 +44,6 @@ uhd.git/
| |
--fx3/ --fx3/
| |
--ad9361/ # From UHD
--b200/ # From UHD --b200/ # From UHD
--common/ # From Cypress SDK --common/ # From Cypress SDK
--gpif2_designer/ # From UHD --gpif2_designer/ # From UHD

16
firmware/fx3/ad9361/include/ad9361_dispatch.h
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@ -1,16 +0,0 @@
//
// Copyright 2013-2014 Ettus Research LLC
//
#ifndef INCLUDED_AD9361_DISPATCH_H
#define INCLUDED_AD9361_DISPATCH_H
#include <ad9361_transaction.h>
extern void ad9361_dispatch(const char* request, char* response);
typedef void (*msgfn)(const char*, ...);
extern void ad9361_set_msgfn(msgfn pfn);
#endif /* INCLUDED_AD9361_DISPATCH_H */

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firmware/fx3/ad9361/include/ad9361_transaction.h
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@ -1,93 +0,0 @@
//
// Copyright 2013-2014 Ettus Research LLC
//
#ifndef INCLUDED_AD9361_TRANSACTION_H
#define INCLUDED_AD9361_TRANSACTION_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
//various constants
#define AD9361_TRANSACTION_VERSION 0x5
#define AD9361_DISPATCH_PACKET_SIZE 64
//action types
#define AD9361_ACTION_ECHO 0
#define AD9361_ACTION_INIT 1
#define AD9361_ACTION_SET_RX1_GAIN 2
#define AD9361_ACTION_SET_TX1_GAIN 3
#define AD9361_ACTION_SET_RX2_GAIN 4
#define AD9361_ACTION_SET_TX2_GAIN 5
#define AD9361_ACTION_SET_RX_FREQ 6
#define AD9361_ACTION_SET_TX_FREQ 7
#define AD9361_ACTION_SET_CODEC_LOOP 8
#define AD9361_ACTION_SET_CLOCK_RATE 9
#define AD9361_ACTION_SET_ACTIVE_CHAINS 10
static inline void ad9361_double_pack(const double input, uint32_t output[2])
{
const uint32_t *p = (const uint32_t *)&input;
output[0] = p[0];
output[1] = p[1];
}
static inline double ad9361_double_unpack(const uint32_t input[2])
{
double output = 0.0;
uint32_t *p = (uint32_t *)&output;
p[0] = input[0];
p[1] = input[1];
return output;
}
typedef struct
{
//version is expected to be AD9361_TRANSACTION_VERSION
//check otherwise for compatibility
uint32_t version;
//sequence number - increment every call for sanity
uint32_t sequence;
//location info for the ad9361 chip class
uint64_t handle;
//action tells us what to do, see AD9361_ACTION_*
uint32_t action;
union
{
//enable mask for chains
uint32_t enable_mask;
//true to enable codec internal loopback
uint32_t codec_loop;
//freq holds request LO freq and result from tune
uint32_t freq[2];
//gain holds request gain and result from action
uint32_t gain[2];
//rate holds request clock rate and result from action
uint32_t rate[2];
} value;
//error message comes back as a reply -
//set to null string for no error \0
char error_msg[];
} ad9361_transaction_t;
#define AD9361_TRANSACTION_MAX_ERROR_MSG (AD9361_DISPATCH_PACKET_SIZE - (sizeof(ad9361_transaction_t)-4)-1) // -4 for 'error_msg' alignment padding, -1 for terminating \0
#ifdef __cplusplus
}
#endif
#endif /* INCLUDED_AD9361_TRANSACTION_H */

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firmware/fx3/ad9361/lib/ad9361_filter_taps.h
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@ -1,47 +0,0 @@
//
// Copyright 2013-2014 Ettus Research LLC
//
#ifndef INCLUDED_AD9361_FILTER_TAPS_HPP
#define INCLUDED_AD9361_FILTER_TAPS_HPP
/* A default 128-tap filter that can be used for generic circumstances. */
static uint16_t default_128tap_coeffs[] = {
0x0001,0xfff1,0xffcf,0xffc0,0xffe8,0x0020,0x001a,0xffe3,
0xffe1,0x001f,0x0028,0xffdf,0xffcc,0x0024,0x0043,0xffdb,
0xffac,0x0026,0x0068,0xffdb,0xff80,0x0022,0x009a,0xffe2,
0xff47,0x0017,0x00db,0xfff3,0xfeff,0xffff,0x012b,0x0013,
0xfea5,0xffd7,0x0190,0x0046,0xfe35,0xff97,0x020e,0x0095,
0xfda7,0xff36,0x02ae,0x010d,0xfcf0,0xfea1,0x0383,0x01c6,
0xfbf3,0xfdb6,0x04b7,0x02f8,0xfa6d,0xfc1a,0x06be,0x0541,
0xf787,0xf898,0x0b60,0x0b6d,0xee88,0xea40,0x2786,0x7209
};
/* The below pair of filters is optimized for a 10MHz LTE application. */
/*
static uint16_t lte10mhz_rx_coeffs[] = {
0xffe2,0x0042,0x0024,0x0095,0x0056,0x004d,0xffcf,0xffb7,
0xffb1,0x0019,0x0059,0x006a,0x0004,0xff9d,0xff72,0xffd4,
0x0063,0x00b7,0x0062,0xffac,0xff21,0xff59,0x0032,0x0101,
0x00f8,0x0008,0xfeea,0xfeac,0xffa3,0x0117,0x01b5,0x00d0,
0xff05,0xfdea,0xfe9e,0x00ba,0x026f,0x0215,0xffb5,0xfd4a,
0xfd18,0xffa0,0x02de,0x03dc,0x0155,0xfd2a,0xfb0d,0xfd54,
0x0287,0x062f,0x048a,0xfe37,0xf862,0xf8c1,0x004d,0x0963,
0x0b88,0x02a4,0xf3e7,0xebdd,0xf5f8,0x1366,0x3830,0x518b
};
static uint16_t lte10mhz_tx_coeffs[] = {
0xfffb,0x0000,0x0004,0x0017,0x0024,0x0028,0x0013,0xfff3,
0xffdc,0xffe5,0x000b,0x0030,0x002e,0xfffe,0xffc4,0xffb8,
0xfff0,0x0045,0x0068,0x002b,0xffb6,0xff72,0xffad,0x0047,
0x00b8,0x0088,0xffc8,0xff1c,0xff33,0x001a,0x0110,0x0124,
0x0019,0xfec8,0xfe74,0xff9a,0x0156,0x0208,0x00d3,0xfe9b,
0xfd68,0xfe96,0x015d,0x033f,0x0236,0xfecd,0xfc00,0xfcb5,
0x00d7,0x04e5,0x04cc,0xffd5,0xf9fe,0xf8fb,0xfef2,0x078c,
0x0aae,0x036d,0xf5c0,0xed89,0xf685,0x12af,0x36a4,0x4faa
};
*/
#endif // INCLUDED_AD9361_FILTER_TAPS_HPP

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firmware/fx3/ad9361/lib/ad9361_gain_tables.h
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@ -1,95 +0,0 @@
//
// Copyright 2013-2014 Ettus Research LLC
//
#ifndef INCLUDED_AD9361_GAIN_TABLES_HPP
#define INCLUDED_AD9361_GAIN_TABLES_HPP
uint8_t gain_table_sub_1300mhz[77][5] = { {0,0x00,0x00,0x20,1},
{1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x01,0x00,0},
{4,0x00,0x02,0x00,0}, {5,0x00,0x03,0x00,0}, {6,0x00,0x04,0x00,0},
{7,0x00,0x05,0x00,0}, {8,0x01,0x03,0x20,1}, {9,0x01,0x04,0x00,0},
{10,0x01,0x05,0x00,0}, {11,0x01,0x06,0x00,0}, {12,0x01,0x07,0x00,0},
{13,0x01,0x08,0x00,0}, {14,0x01,0x09,0x00,0}, {15,0x01,0x0A,0x00,0},
{16,0x01,0x0B,0x00,0}, {17,0x01,0x0C,0x00,0}, {18,0x01,0x0D,0x00,0},
{19,0x01,0x0E,0x00,0}, {20,0x02,0x09,0x20,1}, {21,0x02,0x0A,0x00,0},
{22,0x02,0x0B,0x00,0}, {23,0x02,0x0C,0x00,0}, {24,0x02,0x0D,0x00,0},
{25,0x02,0x0E,0x00,0}, {26,0x02,0x0F,0x00,0}, {27,0x02,0x10,0x00,0},
{28,0x02,0x2B,0x20,1}, {29,0x02,0x2C,0x00,0}, {30,0x04,0x27,0x20,1},
{31,0x04,0x28,0x00,0}, {32,0x04,0x29,0x00,0}, {33,0x04,0x2A,0x00,0},
{34,0x04,0x2B,0x00,1}, {35,0x24,0x21,0x20,0}, {36,0x24,0x22,0x00,1},
{37,0x44,0x20,0x20,0}, {38,0x44,0x21,0x00,0}, {39,0x44,0x22,0x00,0},
{40,0x44,0x23,0x00,0}, {41,0x44,0x24,0x00,0}, {42,0x44,0x25,0x00,0},
{43,0x44,0x26,0x00,0}, {44,0x44,0x27,0x00,0}, {45,0x44,0x28,0x00,0},
{46,0x44,0x29,0x00,0}, {47,0x44,0x2A,0x00,0}, {48,0x44,0x2B,0x00,0},
{49,0x44,0x2C,0x00,0}, {50,0x44,0x2D,0x00,0}, {51,0x44,0x2E,0x00,0},
{52,0x44,0x2F,0x00,0}, {53,0x44,0x30,0x00,0}, {54,0x44,0x31,0x00,0},
{55,0x64,0x2E,0x20,1}, {56,0x64,0x2F,0x00,0}, {57,0x64,0x30,0x00,0},
{58,0x64,0x31,0x00,0}, {59,0x64,0x32,0x00,0}, {60,0x64,0x33,0x00,0},
{61,0x64,0x34,0x00,0}, {62,0x64,0x35,0x00,0}, {63,0x64,0x36,0x00,0},
{64,0x64,0x37,0x00,0}, {65,0x64,0x38,0x00,0}, {66,0x65,0x38,0x20,1},
{67,0x66,0x38,0x20,1}, {68,0x67,0x38,0x20,1}, {69,0x68,0x38,0x20,1},
{70,0x69,0x38,0x20,1}, {71,0x6A,0x38,0x20,1}, {72,0x6B,0x38,0x20,1},
{73,0x6C,0x38,0x20,1}, {74,0x6D,0x38,0x20,1}, {75,0x6E,0x38,0x20,1},
{76,0x6F,0x38,0x20,1}};
uint8_t gain_table_1300mhz_to_4000mhz[77][5] = { {0,0x00,0x00,0x20,1},
{1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x01,0x00,0},
{4,0x00,0x02,0x00,0}, {5,0x00,0x03,0x00,0}, {6,0x00,0x04,0x00,0},
{7,0x00,0x05,0x00,0}, {8,0x01,0x03,0x20,1}, {9,0x01,0x04,0x00,0},
{10,0x01,0x05,0x00,0}, {11,0x01,0x06,0x00,0}, {12,0x01,0x07,0x00,0},
{13,0x01,0x08,0x00,0}, {14,0x01,0x09,0x00,0}, {15,0x01,0x0A,0x00,0},
{16,0x01,0x0B,0x00,0}, {17,0x01,0x0C,0x00,0}, {18,0x01,0x0D,0x00,0},
{19,0x01,0x0E,0x00,0}, {20,0x02,0x09,0x20,1}, {21,0x02,0x0A,0x00,0},
{22,0x02,0x0B,0x00,0}, {23,0x02,0x0C,0x00,0}, {24,0x02,0x0D,0x00,0},
{25,0x02,0x0E,0x00,0}, {26,0x02,0x0F,0x00,0}, {27,0x02,0x10,0x00,0},
{28,0x02,0x2B,0x20,1}, {29,0x02,0x2C,0x00,0}, {30,0x04,0x28,0x20,1},
{31,0x04,0x29,0x00,0}, {32,0x04,0x2A,0x00,0}, {33,0x04,0x2B,0x00,0},
{34,0x24,0x20,0x20,0}, {35,0x24,0x21,0x00,1}, {36,0x44,0x20,0x20,0},
{37,0x44,0x21,0x00,1}, {38,0x44,0x22,0x00,0}, {39,0x44,0x23,0x00,0},
{40,0x44,0x24,0x00,0}, {41,0x44,0x25,0x00,0}, {42,0x44,0x26,0x00,0},
{43,0x44,0x27,0x00,0}, {44,0x44,0x28,0x00,0}, {45,0x44,0x29,0x00,0},
{46,0x44,0x2A,0x00,0}, {47,0x44,0x2B,0x00,0}, {48,0x44,0x2C,0x00,0},
{49,0x44,0x2D,0x00,0}, {50,0x44,0x2E,0x00,0}, {51,0x44,0x2F,0x00,0},
{52,0x44,0x30,0x00,0}, {53,0x44,0x31,0x00,0}, {54,0x44,0x32,0x00,0},
{55,0x64,0x2E,0x20,1}, {56,0x64,0x2F,0x00,0}, {57,0x64,0x30,0x00,0},
{58,0x64,0x31,0x00,0}, {59,0x64,0x32,0x00,0}, {60,0x64,0x33,0x00,0},
{61,0x64,0x34,0x00,0}, {62,0x64,0x35,0x00,0}, {63,0x64,0x36,0x00,0},
{64,0x64,0x37,0x00,0}, {65,0x64,0x38,0x00,0}, {66,0x65,0x38,0x20,1},
{67,0x66,0x38,0x20,1}, {68,0x67,0x38,0x20,1}, {69,0x68,0x38,0x20,1},
{70,0x69,0x38,0x20,1}, {71,0x6A,0x38,0x20,1}, {72,0x6B,0x38,0x20,1},
{73,0x6C,0x38,0x20,1}, {74,0x6D,0x38,0x20,1}, {75,0x6E,0x38,0x20,1},
{76,0x6F,0x38,0x20,1}};
uint8_t gain_table_4000mhz_to_6000mhz[77][5] = { {0,0x00,0x00,0x20,1},
{1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x00,0x00,0},
{4,0x00,0x00,0x00,0}, {5,0x00,0x01,0x00,0}, {6,0x00,0x02,0x00,0},
{7,0x00,0x03,0x00,0}, {8,0x01,0x01,0x20,1}, {9,0x01,0x02,0x00,0},
{10,0x01,0x03,0x00,0}, {11,0x01,0x04,0x20,1}, {12,0x01,0x05,0x00,0},
{13,0x01,0x06,0x00,0}, {14,0x01,0x07,0x00,0}, {15,0x01,0x08,0x00,0},
{16,0x01,0x09,0x00,0}, {17,0x01,0x0A,0x00,0}, {18,0x01,0x0B,0x00,0},
{19,0x01,0x0C,0x00,0}, {20,0x02,0x08,0x20,1}, {21,0x02,0x09,0x00,0},
{22,0x02,0x0A,0x00,0}, {23,0x02,0x0B,0x20,1}, {24,0x02,0x0C,0x00,0},
{25,0x02,0x0D,0x00,0}, {26,0x02,0x0E,0x00,0}, {27,0x02,0x0F,0x00,0},
{28,0x02,0x2A,0x20,1}, {29,0x02,0x2B,0x00,0}, {30,0x04,0x27,0x20,1},
{31,0x04,0x28,0x00,0}, {32,0x04,0x29,0x00,0}, {33,0x04,0x2A,0x00,0},
{34,0x04,0x2B,0x00,0}, {35,0x04,0x2C,0x00,0}, {36,0x04,0x2D,0x00,0},
{37,0x24,0x20,0x20,1}, {38,0x24,0x21,0x00,0}, {39,0x24,0x22,0x00,0},
{40,0x44,0x20,0x20,1}, {41,0x44,0x21,0x00,0}, {42,0x44,0x22,0x00,0},
{43,0x44,0x23,0x00,0}, {44,0x44,0x24,0x00,0}, {45,0x44,0x25,0x00,0},
{46,0x44,0x26,0x00,0}, {47,0x44,0x27,0x00,0}, {48,0x44,0x28,0x00,0},
{49,0x44,0x29,0x00,0}, {50,0x44,0x2A,0x00,0}, {51,0x44,0x2B,0x00,0},
{52,0x44,0x2C,0x00,0}, {53,0x44,0x2D,0x00,0}, {54,0x44,0x2E,0x00,0},
{55,0x64,0x2E,0x20,1}, {56,0x64,0x2F,0x00,0}, {57,0x64,0x30,0x00,0},
{58,0x64,0x31,0x00,0}, {59,0x64,0x32,0x00,0}, {60,0x64,0x33,0x00,0},
{61,0x64,0x34,0x00,0}, {62,0x64,0x35,0x00,0}, {63,0x64,0x36,0x00,0},
{64,0x64,0x37,0x00,0}, {65,0x64,0x38,0x00,0}, {66,0x65,0x38,0x20,1},
{67,0x66,0x38,0x20,1}, {68,0x67,0x38,0x20,1}, {69,0x68,0x38,0x20,1},
{70,0x69,0x38,0x20,1}, {71,0x6A,0x38,0x20,1}, {72,0x6B,0x38,0x20,1},
{73,0x6C,0x38,0x20,1}, {74,0x6D,0x38,0x20,1}, {75,0x6E,0x38,0x20,1},
{76,0x6F,0x38,0x20,1}};
#endif /* INCLUDED_AD9361_GAIN_TABLES_HPP */

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firmware/fx3/ad9361/lib/ad9361_impl.c
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firmware/fx3/ad9361/lib/ad9361_synth_lut.h
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//
// Copyright 2013-2014 Ettus Research LLC
//
#ifndef INCLUDED_AD9361_SYNTH_LUT_HPP
#define INCLUDED_AD9361_SYNTH_LUT_HPP
double vco_index[53] = {12605000000, 12245000000, 11906000000, 11588000000,
11288000000, 11007000000, 10742000000, 10492000000,
10258000000, 10036000000, 9827800000, 9631100000,
9445300000, 9269800000, 9103600000, 8946300000,
8797000000, 8655300000, 8520600000, 8392300000,
8269900000, 8153100000, 8041400000, 7934400000,
7831800000, 7733200000, 7638400000, 7547100000,
7459000000, 7374000000, 7291900000, 7212400000,
7135500000, 7061000000, 6988700000, 6918600000,
6850600000, 6784600000, 6720500000, 6658200000,
6597800000, 6539200000, 6482300000, 6427000000,
6373400000, 6321400000, 6270900000, 6222000000,
6174500000, 6128400000, 6083600000, 6040100000,
5997700000};
int synth_cal_lut[53][12] = { {10, 0, 4, 0, 15, 8, 8, 13, 4, 13, 15, 9},
{10, 0, 4, 0, 15, 8, 9, 13, 4, 13, 15, 9},
{10, 0, 4, 0, 15, 8, 10, 13, 4, 13, 15, 9},
{10, 0, 4, 0, 15, 8, 11, 13, 4, 13, 15, 9},
{10, 0, 4, 0, 15, 8, 11, 13, 4, 13, 15, 9},
{10, 0, 4, 0, 14, 8, 12, 13, 4, 13, 15, 9},
{10, 0, 4, 0, 14, 8, 13, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 14, 9, 13, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 14, 9, 14, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 14, 9, 15, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 14, 9, 15, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 13, 9, 16, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 13, 9, 17, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 13, 9, 18, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 13, 9, 18, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 13, 9, 19, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 14, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 14, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 15, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 15, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 16, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 16, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 17, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 17, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 18, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 18, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 19, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 19, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 20, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 12, 20, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 12, 21, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 12, 21, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 22, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 22, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 23, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 23, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 24, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 24, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 25, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 25, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 26, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 26, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 27, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 27, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 18, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 18, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 18, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 20, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 20, 13, 4, 13, 15, 9}};
#if 0 /* This is the table for a 40MHz RFPLL Reference */
int synth_cal_lut[53][12] = { {10, 0, 4, 0, 15, 8, 8, 12, 3, 14, 15, 11},
{10, 0, 4, 0, 15, 8, 9, 12, 3, 14, 15, 11},
{10, 0, 4, 0, 15, 8, 9, 12, 3, 14, 15, 11},
{10, 0, 4, 0, 15, 8, 10, 12, 3, 14, 15, 11},
{10, 0, 4, 0, 15, 8, 11, 12, 3, 14, 15, 11},
{10, 0, 4, 0, 15, 8, 11, 12, 3, 14, 15, 11},
{10, 0, 4, 0, 14, 8, 12, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 13, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 13, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 14, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 15, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 15, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 16, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 17, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 17, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 18, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 13, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 14, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 14, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 15, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 15, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 16, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 16, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 17, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 17, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 17, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 18, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 18, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 19, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 12, 19, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 12, 20, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 12, 20, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 21, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 21, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 22, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 22, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 23, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 23, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 24, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 24, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 25, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 25, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 26, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 26, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 17, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 17, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 17, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 19, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 19, 12, 3, 14, 15, 11} };
#endif
#endif /* INCLUDED_AD9361_SYNTH_LUT_HPP */

57
firmware/fx3/b200/b200_ad9361.c
View File

@ -1,57 +0,0 @@
//
// Copyright 2013-2014 Ettus Research LLC
//
#include "cyu3error.h"
#include "cyu3i2c.h"
#include "cyu3spi.h"
#include "cyu3os.h"
#include "cyu3pib.h"
#include "cyu3system.h"
#include "cyu3usb.h"
#include "cyu3utils.h"
#include "pib_regs.h"
#include "b200_vrq.h"
#include <stdint.h>
#define true CyTrue
#define false CyFalse
typedef CyBool_t bool;
/* Fast sqrt() - precision can be improved by increasing
* the number of iterations
*/
float ad9361_sqrt(const float number)
{
uint32_t i;
float x2, y;
x2 = number * 0.5F;
y = number;
i = *(uint32_t *) &y;
i = 0x5f3759df - ( i >> 1 );
y = *(float *) &i;
y = y * (1.5F - (x2 * y * y));
return number * y;
}
void ad9361_msleep(const unsigned millis)
{
CyU3PThreadSleep(millis);
}
#define AD9361_MIN(a, b) CY_U3P_MIN(a, b)
#define AD9361_MAX(a, b) CY_U3P_MAX(a, b)
#define AD9361_CEIL_INT(a) ((int)(a+1))
#define AD9361_FLOOR_INT(a) ((int)(a))
#define AD9361_CLOCKING_MODE 0
#define AD9361_RX_BAND_EDGE0 2.2e9
#define AD9361_RX_BAND_EDGE1 4e9
#define AD9361_TX_BAND_EDGE 2.5e9
#include "../ad9361/lib/ad9361_impl.c"

328
firmware/fx3/b200/b200_main.c
View File

@ -12,7 +12,6 @@
#include "b200_main.h" #include "b200_main.h"
#include "b200_gpifconfig.h" #include "b200_gpifconfig.h"
#include "b200_vrq.h"
#include "b200_i2c.h" #include "b200_i2c.h"
#include "cyu3dma.h" #include "cyu3dma.h"
@ -28,9 +27,6 @@
#include "cyfxversion.h" #include "cyfxversion.h"
#include "pib_regs.h" #include "pib_regs.h"
#include <ad9361_transaction.h>
#include <ad9361_dispatch.h>
#define STATIC_SAVER static // Save stack space for variables in a non-re-entrant function (e.g. USB setup callback) #define STATIC_SAVER static // Save stack space for variables in a non-re-entrant function (e.g. USB setup callback)
/* /*
@ -40,7 +36,6 @@
//#define HAS_HEAP // This requires memory to be set aside for the heap (e.g. required for printing floating-point numbers). You can apply the accompanying patch ('fx3_mem_map.patch') to fx3.ld & cyfxtx.c to create one. //#define HAS_HEAP // This requires memory to be set aside for the heap (e.g. required for printing floating-point numbers). You can apply the accompanying patch ('fx3_mem_map.patch') to fx3.ld & cyfxtx.c to create one.
//#define ENABLE_MSG // This will cause the compiled code to exceed the default text memory area (SYS_MEM). You can apply the accompanying patch ('fx3_mem_map.patch') to fx3.ld & cyfxtx.c to resize the memory map so it will fit. //#define ENABLE_MSG // This will cause the compiled code to exceed the default text memory area (SYS_MEM). You can apply the accompanying patch ('fx3_mem_map.patch') to fx3.ld & cyfxtx.c to resize the memory map so it will fit.
//#define ENABLE_AD9361_LOGGING // When enabling this, you *must* enable the heap with HAS_HEAP (and apply the accompanying memory map patch 'fx3_mem_map.patch') otherwise the FW will crash when printing a floating-point number (as there is no heap for _sbrk by default)
//#define ENABLE_MANUAL_DMA_XFER //#define ENABLE_MANUAL_DMA_XFER
//#define ENABLE_MANUAL_DMA_XFER_FROM_HOST //#define ENABLE_MANUAL_DMA_XFER_FROM_HOST
//#define ENABLE_MANUAL_DMA_XFER_TO_HOST //#define ENABLE_MANUAL_DMA_XFER_TO_HOST
@ -69,13 +64,6 @@
#ifdef ENABLE_MSG #ifdef ENABLE_MSG
#pragma message "msg enabled" #pragma message "msg enabled"
#ifdef ENABLE_AD9361_LOGGING
#pragma message " AD9361 logging enabled"
#else
#pragma message " AD9361 logging disabled"
#endif // ENABLE_AD9361_LOGGING
#else #else
#pragma message "msg disabled" #pragma message "msg disabled"
#endif // ENABLE_MSG #endif // ENABLE_MSG
@ -156,21 +144,15 @@ static CyU3PThread thread_fpga_config;
#ifdef ENABLE_RE_ENUM_THREAD #ifdef ENABLE_RE_ENUM_THREAD
static CyU3PThread thread_re_enum; static CyU3PThread thread_re_enum;
#endif // ENABLE_RE_ENUM_THREAD #endif // ENABLE_RE_ENUM_THREAD
static CyU3PThread thread_ad9361;
static CyBool_t g_app_running = CyFalse; static CyBool_t g_app_running = CyFalse;
static uint8_t g_fx3_state = STATE_UNDEFINED; static uint8_t g_fx3_state = STATE_UNDEFINED;
//#define AD9361_DISPATCH_PACKET_SIZE 64 // Must fit into smallest VREQ
#define USB2_VREQ_BUF_SIZE 64 #define USB2_VREQ_BUF_SIZE 64
#define USB3_VREQ_BUF_SIZE 512 #define USB3_VREQ_BUF_SIZE 512
#define MIN_VREQ_BUF_SIZE USB2_VREQ_BUF_SIZE #define MIN_VREQ_BUF_SIZE USB2_VREQ_BUF_SIZE
#define MAX_VREQ_BUF_SIZE USB3_VREQ_BUF_SIZE #define MAX_VREQ_BUF_SIZE USB3_VREQ_BUF_SIZE
#if AD9361_DISPATCH_PACKET_SIZE > MIN_VREQ_BUF_SIZE
#error "AD9361_DISPATCH_PACKET_SIZE must be less than MIN_VREQ_BUF_SIZE"
#endif
static uint16_t g_vendor_req_buff_size = MIN_VREQ_BUF_SIZE; static uint16_t g_vendor_req_buff_size = MIN_VREQ_BUF_SIZE;
static uint8_t g_vendor_req_buffer[MAX_VREQ_BUF_SIZE] __attribute__ ((aligned (32))); static uint8_t g_vendor_req_buffer[MAX_VREQ_BUF_SIZE] __attribute__ ((aligned (32)));
static uint16_t g_vendor_req_read_count = 0; static uint16_t g_vendor_req_read_count = 0;
@ -180,8 +162,6 @@ static uint8_t fw_hash[4] __attribute__ ((aligned (32)));
static uint8_t compat_num[2]; static uint8_t compat_num[2];
static uint32_t g_fpga_programming_write_count = 0; static uint32_t g_fpga_programming_write_count = 0;
static char g_ad9361_response[AD9361_DISPATCH_PACKET_SIZE];
#define COUNTER_MAGIC 0x10024001 #define COUNTER_MAGIC 0x10024001
#define LOG_BUFFER_SIZE /*MAX_VREQ_BUF_SIZE*/1024 // [Max vreq @ USB3 (64 @ USB2)] Can be larger #define LOG_BUFFER_SIZE /*MAX_VREQ_BUF_SIZE*/1024 // [Max vreq @ USB3 (64 @ USB2)] Can be larger
static char log_buffer[LOG_BUFFER_SIZE]; static char log_buffer[LOG_BUFFER_SIZE];
@ -685,214 +665,6 @@ void gpio_interrupt_callback(uint8_t gpio_id) {
} }
// The following two functions are intended to replace write_spi_to_ad9361
// and read_spi_from_ad9361 after the code porting is complete
/*! Perform a register write to the ad9361 chip.
* A pointer to the register address followed by data will be provided as
* parameter
*/
static void write_ad9361_reg(uint16_t reg, uint8_t val) {
CyBool_t gpio_value;
uint8_t write_buff[3];
MAKE_AD9361_WRITE(write_buff, reg, val)
// Number of bytes we are writing.
uint8_t num_bytes = 3; //register address = 2 bytes, data = 1 byte
CyU3PGpioSetValue(GPIO_FX3_CE, 0);
// Clock the data out to AD9361 over SPI.
int8_t bit_count, byte_count;
for(byte_count = 0; byte_count < num_bytes; byte_count++) {
uint8_t miso = 0x00;
uint8_t data = write_buff[byte_count];
for(bit_count = 7; bit_count >= 0; bit_count--) {
CyU3PGpioSetValue(GPIO_FX3_SCLK, 1);
CyU3PGpioSetValue(GPIO_FX3_MOSI, ((data >> bit_count) & 0x01));
CyU3PGpioSetValue(GPIO_FX3_SCLK, 0);
CyU3PGpioGetValue(GPIO_FX3_MISO, &gpio_value);
if(gpio_value) {
miso |= (1 << bit_count);
}
}
// FIXME: Determine what to do with miso value;
}
CyU3PGpioSetValue(GPIO_FX3_MOSI, 0);
CyU3PGpioSetValue(GPIO_FX3_CE, 1);
}
/*! Perform a register read from to the ad9361 chip.
* A pointer to register address will be provided as parameter
* The function returns the value read from the register
*/
static uint8_t read_ad9361_reg(uint16_t reg) {
CyBool_t gpio_value;
uint8_t write_buff[2];
MAKE_AD9361_READ(write_buff, reg)
// Each 9361 register read returns 1 byte
CyU3PGpioSetValue(GPIO_FX3_CE, 0);
// Write the two register address bytes.
int8_t bit_count, byte_count;
for(byte_count = 0; byte_count < 2; byte_count++) {
uint8_t miso = 0x00;
uint8_t data = write_buff[byte_count];
for(bit_count = 7; bit_count >= 0; bit_count--) {
CyU3PGpioSetValue(GPIO_FX3_SCLK, 1);
CyU3PGpioSetValue(GPIO_FX3_MOSI, ((data >> bit_count) & 0x01));
CyU3PGpioSetValue(GPIO_FX3_SCLK, 0);
CyU3PGpioGetValue(GPIO_FX3_MISO, &gpio_value);
if(gpio_value) {
miso |= (1 << bit_count);
}
}
// FIXME: Determine what to do with miso value;
}
CyU3PGpioSetValue(GPIO_FX3_MOSI, 0);
// Read the response data from the chip.
uint8_t data = 0x00;
for(bit_count = 7; bit_count >= 0; bit_count--) {
CyU3PGpioSetValue(GPIO_FX3_SCLK, 1);
CyU3PGpioGetValue(GPIO_FX3_MISO, &gpio_value);
if(gpio_value) {
data |= (1 << bit_count);
}
CyU3PGpioSetValue(GPIO_FX3_SCLK, 0);
}
CyU3PGpioSetValue(GPIO_FX3_CE, 1);
return data;
}
/*! Perform a register write to the ad9361 chip.
*
* This function will take data received over EP0, as a vendor request, and
* perform a SPI write to ad9361. This requires that the FPGA be passing these
* SPI lines through to the ad9361 chip. */
void write_spi_to_ad9361(void) {
CyBool_t gpio_value;
/* Pull out the number of bytes we are writing. */
uint8_t num_bytes = ((g_vendor_req_buffer[0] & 0x70) >> 4) + 1;
CyU3PGpioSetValue(GPIO_FX3_CE, 0);
/* Clock the data out to AD9361 over SPI. */
int8_t bit_count, byte_count;
for(byte_count = 0; byte_count < (num_bytes + 2); byte_count++) {
uint8_t miso = 0x00;
uint8_t data = g_vendor_req_buffer[byte_count];
for(bit_count = 7; bit_count >= 0; bit_count--) {
CyU3PGpioSetValue(GPIO_FX3_SCLK, 1);
CyU3PGpioSetValue(GPIO_FX3_MOSI, ((data >> bit_count) & 0x01));
CyU3PGpioSetValue(GPIO_FX3_SCLK, 0);
CyU3PGpioGetValue(GPIO_FX3_MISO, &gpio_value);
if(gpio_value) {
miso |= (1 << bit_count);
}
}
g_vendor_req_buffer[byte_count] = miso;
}
CyU3PGpioSetValue(GPIO_FX3_MOSI, 0);
CyU3PGpioSetValue(GPIO_FX3_CE, 1);
}
/*! Perform a register read from the ad9361 chip.
*
* This function will write a command to the ad9361 chip, performing a register
* read, and store the returned data in the vendor request buffer. This data can
* then be retrieved with another vendor request from the host.
*
* This requires that the FPGA be passing these SPI lines through to the
* ad9361 chip. */
void read_spi_from_ad9361(void) {
CyBool_t gpio_value;
/* Pull out the number of bytes we are reading. */
uint8_t num_bytes = ((g_vendor_req_buffer[0] & 0x70) >> 4) + 1;
CyU3PGpioSetValue(GPIO_FX3_CE, 0);
/* Write the two instruction bytes. */
int8_t bit_count, byte_count;
for(byte_count = 0; byte_count < 2; byte_count++) {
uint8_t miso = 0x00;
uint8_t data = g_vendor_req_buffer[byte_count];
for(bit_count = 7; bit_count >= 0; bit_count--) {
CyU3PGpioSetValue(GPIO_FX3_SCLK, 1);
CyU3PGpioSetValue(GPIO_FX3_MOSI, ((data >> bit_count) & 0x01));
CyU3PGpioSetValue(GPIO_FX3_SCLK, 0);
CyU3PGpioGetValue(GPIO_FX3_MISO, &gpio_value);
if(gpio_value) {
miso |= (1 << bit_count);
}
}
g_vendor_req_buffer[byte_count] = miso;
}
CyU3PGpioSetValue(GPIO_FX3_MOSI, 0);
/* Read the response data from the chip. */
for(byte_count = 0; byte_count < num_bytes; byte_count++) {
uint8_t data = 0x00;
for(bit_count = 7; bit_count >= 0; bit_count--) {
CyU3PGpioSetValue(GPIO_FX3_SCLK, 1);
CyU3PGpioGetValue(GPIO_FX3_MISO, &gpio_value);
if(gpio_value) {
data |= (1 << bit_count);
}
CyU3PGpioSetValue(GPIO_FX3_SCLK, 0);
}
g_vendor_req_buffer[byte_count + 2] = data;
}
CyU3PGpioSetValue(GPIO_FX3_CE, 1);
}
uint32_t ad9361_transact_spi(const uint32_t bits) {
// FIXME: Could make this more sane
if ((bits >> 23) & 0x1)
{
write_ad9361_reg(bits >> 8, bits & 0xff);
return 0;
}
return read_ad9361_reg(bits >> 8);
}
/*! Stops the application, and destroys transport data structures. /*! Stops the application, and destroys transport data structures.
* *
* This function is essentially a destructor for all transport configurations. * This function is essentially a destructor for all transport configurations.
@ -1891,22 +1663,6 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) {
break; break;
} }
case B200_VREQ_SPI_WRITE_AD9361: {
CyU3PUsbGetEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer, \
&read_count);
write_spi_to_ad9361(); // FIXME: Should have g_vendor_req_buffer & read_count passed in as args
break;
}
case B200_VREQ_SPI_READ_AD9361: {
CyU3PUsbGetEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer, \
&read_count);
read_spi_from_ad9361(); // FIXME: Should have g_vendor_req_buffer & read_count passed in as args
break;
}
case B200_VREQ_LOOP_CODE: { case B200_VREQ_LOOP_CODE: {
CyU3PUsbSendEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer); CyU3PUsbSendEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer);
break; break;
@ -2152,55 +1908,6 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) {
break; break;
} }
case B200_VREQ_AD9361_CTRL_READ: {
CyU3PUsbSendEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer);
/*
* This is where vrb gets sent back to the host
*/
break;
}
case B200_VREQ_AD9361_CTRL_WRITE: {
CyU3PUsbGetEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer, &read_count);
CyU3PEventSet(&g_event_usb_config, EVENT_AD9361_XACT_INIT, CYU3P_EVENT_OR);
uint32_t event_flag;
CyU3PEventGet(&g_event_usb_config, EVENT_AD9361_XACT_DONE, CYU3P_EVENT_AND_CLEAR, &event_flag, CYU3P_WAIT_FOREVER);
memcpy(g_vendor_req_buffer, g_ad9361_response, AD9361_DISPATCH_PACKET_SIZE);
break;
}
case B200_VREQ_AD9361_LOOPBACK: {
CyU3PUsbGetEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer, &read_count);
if (read_count > 0) {
ad9361_transaction_t xact;
memset(&xact, 0x00, sizeof(xact));
xact.version = AD9361_TRANSACTION_VERSION;
xact.action = AD9361_ACTION_SET_CODEC_LOOP;
xact.sequence = 0;
xact.value.codec_loop = g_vendor_req_buffer[0];
memcpy(g_vendor_req_buffer, &xact, sizeof(xact));
CyU3PEventSet(&g_event_usb_config, EVENT_AD9361_XACT_INIT, CYU3P_EVENT_OR);
uint32_t event_flag;
CyU3PEventGet(&g_event_usb_config, EVENT_AD9361_XACT_DONE, CYU3P_EVENT_AND_CLEAR, &event_flag, CYU3P_WAIT_FOREVER);
memcpy(g_vendor_req_buffer, g_ad9361_response, AD9361_DISPATCH_PACKET_SIZE);
if (xact.value.codec_loop)
msg("Codec loopback ON");
else
msg("Codec loopback OFF");
}
break;
}
default: default:
msg("! Unknown VREQ %02X", (uint32_t)bRequest); msg("! Unknown VREQ %02X", (uint32_t)bRequest);
handled = CyFalse; handled = CyFalse;
@ -2684,23 +2391,6 @@ void thread_main_app_entry(uint32_t input) {
} }
} }
void thread_ad9361_entry(uint32_t input) {
uint32_t event_flag;
//msg("thread_ad9361_entry");
while (1) {
if (CyU3PEventGet(&g_event_usb_config, \
EVENT_AD9361_XACT_INIT, CYU3P_EVENT_AND_CLEAR, \
&event_flag, CYU3P_WAIT_FOREVER) == CY_U3P_SUCCESS) {
ad9361_dispatch((const char*)g_vendor_req_buffer, g_ad9361_response);
CyU3PEventSet(&g_event_usb_config, EVENT_AD9361_XACT_DONE, CYU3P_EVENT_OR);
}
}
}
static uint16_t g_poll_last_phy_error_count = 0, g_poll_last_link_error_count = 0; static uint16_t g_poll_last_phy_error_count = 0, g_poll_last_link_error_count = 0;
static uint32_t g_poll_last_phy_error_status = 0; static uint32_t g_poll_last_phy_error_status = 0;
@ -2966,7 +2656,7 @@ void thread_fpga_sb_poll_entry(uint32_t input) {
* If thread creation fails, lock the system and force a power reset. * If thread creation fails, lock the system and force a power reset.
*/ */
void CyFxApplicationDefine(void) { void CyFxApplicationDefine(void) {
void *app_thread_ptr, *fpga_thread_ptr, *ad9361_thread_ptr; void *app_thread_ptr, *fpga_thread_ptr;
#ifdef ENABLE_RE_ENUM_THREAD #ifdef ENABLE_RE_ENUM_THREAD
void *re_enum_thread_ptr; void *re_enum_thread_ptr;
#endif // ENABLE_RE_ENUM_THREAD #endif // ENABLE_RE_ENUM_THREAD
@ -2975,9 +2665,6 @@ void CyFxApplicationDefine(void) {
#endif // ENABLE_FPGA_SB #endif // ENABLE_FPGA_SB
g_counters.magic = COUNTER_MAGIC; g_counters.magic = COUNTER_MAGIC;
#ifdef ENABLE_AD9361_LOGGING
ad9361_set_msgfn(msg);
#endif // ENABLE_AD9361_LOGGING
memset(&g_config, 0xFF, sizeof(g_config)); // Initialise to -1 memset(&g_config, 0xFF, sizeof(g_config)); // Initialise to -1
CyU3PMutexCreate(&g_log_lock, CYU3P_NO_INHERIT); CyU3PMutexCreate(&g_log_lock, CYU3P_NO_INHERIT);
@ -3032,7 +2719,6 @@ void CyFxApplicationDefine(void) {
#ifdef ENABLE_RE_ENUM_THREAD #ifdef ENABLE_RE_ENUM_THREAD
re_enum_thread_ptr = CyU3PMemAlloc(APP_THREAD_STACK_SIZE); re_enum_thread_ptr = CyU3PMemAlloc(APP_THREAD_STACK_SIZE);
#endif // ENABLE_RE_ENUM_THREAD #endif // ENABLE_RE_ENUM_THREAD
ad9361_thread_ptr = CyU3PMemAlloc(APP_THREAD_STACK_SIZE);
#ifdef ENABLE_FPGA_SB #ifdef ENABLE_FPGA_SB
fpga_sb_poll_thread_ptr = CyU3PMemAlloc(APP_THREAD_STACK_SIZE); fpga_sb_poll_thread_ptr = CyU3PMemAlloc(APP_THREAD_STACK_SIZE);
#endif // ENABLE_FPGA_SB #endif // ENABLE_FPGA_SB
@ -3077,18 +2763,6 @@ void CyFxApplicationDefine(void) {
CYU3P_NO_TIME_SLICE, CYU3P_NO_TIME_SLICE,
CYU3P_AUTO_START); CYU3P_AUTO_START);
#endif // ENABLE_RE_ENUM_THREAD #endif // ENABLE_RE_ENUM_THREAD
/* Create thread to handle AD9361 transactions */
if (ad9361_thread_ptr != NULL)
CyU3PThreadCreate(&thread_ad9361,
"500:B200 AD9361",
thread_ad9361_entry,
0,
ad9361_thread_ptr,
APP_THREAD_STACK_SIZE,
THREAD_PRIORITY,
THREAD_PRIORITY,
CYU3P_NO_TIME_SLICE,
CYU3P_AUTO_START);
#ifdef ENABLE_FPGA_SB #ifdef ENABLE_FPGA_SB
/* Create thread to handling Settings Bus logging/transactions */ /* Create thread to handling Settings Bus logging/transactions */
if (fpga_sb_poll_thread_ptr != NULL) if (fpga_sb_poll_thread_ptr != NULL)

9
firmware/fx3/b200/b200_main.h
View File

@ -10,7 +10,7 @@
#include "cyu3types.h" #include "cyu3types.h"
#include "cyu3usbconst.h" #include "cyu3usbconst.h"
#define FX3_COMPAT_MAJOR (uint8_t)(5) #define FX3_COMPAT_MAJOR (uint8_t)(6)
#define FX3_COMPAT_MINOR (uint8_t)(0) #define FX3_COMPAT_MINOR (uint8_t)(0)
/* GPIO Pins */ /* GPIO Pins */
@ -67,16 +67,11 @@
#define B200_VREQ_WRITE_SB (uint8_t)(0x29) #define B200_VREQ_WRITE_SB (uint8_t)(0x29)
#define B200_VREQ_SET_SB_BAUD_DIV (uint8_t)(0x30) #define B200_VREQ_SET_SB_BAUD_DIV (uint8_t)(0x30)
#define B200_VREQ_FLUSH_DATA_EPS (uint8_t)(0x31) #define B200_VREQ_FLUSH_DATA_EPS (uint8_t)(0x31)
#define B200_VREQ_SPI_WRITE_AD9361 (uint8_t)(0x32)
#define B200_VREQ_SPI_READ_AD9361 (uint8_t)(0x42)
#define B200_VREQ_FPGA_CONFIG (uint8_t)(0x55) #define B200_VREQ_FPGA_CONFIG (uint8_t)(0x55)
#define B200_VREQ_TOGGLE_FPGA_RESET (uint8_t)(0x62) #define B200_VREQ_TOGGLE_FPGA_RESET (uint8_t)(0x62)
#define B200_VREQ_TOGGLE_GPIF_RESET (uint8_t)(0x72) #define B200_VREQ_TOGGLE_GPIF_RESET (uint8_t)(0x72)
#define B200_VREQ_GET_USB_SPEED (uint8_t)(0x80) #define B200_VREQ_GET_USB_SPEED (uint8_t)(0x80)
#define B200_VREQ_GET_STATUS (uint8_t)(0x83) #define B200_VREQ_GET_STATUS (uint8_t)(0x83)
#define B200_VREQ_AD9361_CTRL_WRITE (uint8_t)(0x90)
#define B200_VREQ_AD9361_CTRL_READ (uint8_t)(0x91)
#define B200_VREQ_AD9361_LOOPBACK (uint8_t)(0x92)
#define B200_VREQ_RESET_DEVICE (uint8_t)(0x99) #define B200_VREQ_RESET_DEVICE (uint8_t)(0x99)
#define B200_VREQ_EEPROM_WRITE (uint8_t)(0xBA) #define B200_VREQ_EEPROM_WRITE (uint8_t)(0xBA)
#define B200_VREQ_EEPROM_READ (uint8_t)(0xBB) #define B200_VREQ_EEPROM_READ (uint8_t)(0xBB)
@ -86,8 +81,6 @@
#define EVENT_GPIO_INITB_RISE (1 << 3) #define EVENT_GPIO_INITB_RISE (1 << 3)
#define EVENT_FPGA_CONFIG (1 << 4) #define EVENT_FPGA_CONFIG (1 << 4)
#define EVENT_RE_ENUM (1 << 5) #define EVENT_RE_ENUM (1 << 5)
#define EVENT_AD9361_XACT_INIT (1 << 6)
#define EVENT_AD9361_XACT_DONE (1 << 7)
/* FX3 States */ /* FX3 States */

21
firmware/fx3/b200/b200_vrq.h
View File

@ -1,21 +0,0 @@
//
// Copyright 2013-2014 Ettus Research LLC
//
/* This file defines b200 vendor requests handlers, version 1
*/
#ifndef B200_VRQ_H
#define B200_VRQ_H
uint32_t ad9361_transact_spi(const uint32_t bits);
// note: for a write instruction bit 7 from byte 0 is set to 1
#define MAKE_AD9361_WRITE(dest, reg, val) {dest[0] = 0x80 | ((reg >> 8) & 0x3F); \
dest[1] = reg & 0xFF; \
dest[2] = val;}
#define MAKE_AD9361_READ(dest, reg) {dest[0] = (reg >> 8) & 0x3F; \
dest[1] = reg & 0xFF;}
#endif //B200_VRQ_H

6
firmware/fx3/b200/makefile
View File

@ -19,13 +19,9 @@ MODULE = b200_main
SOURCE += $(MODULE).c SOURCE += $(MODULE).c
SOURCE += b200_usb_descriptors.c SOURCE += b200_usb_descriptors.c
SOURCE += b200_ad9361.c
SOURCE += b200_i2c.c SOURCE += b200_i2c.c
INCLUDES = b200_main.h b200_vrq.h b200_gpifconfig.h b200_i2c.h INCLUDES = b200_main.h b200_gpifconfig.h b200_i2c.h
INCLUDES += ../ad9361/include/ad9361_transaction.h
INCFLAGS = -I ../ad9361/include
LDLIBS += \ LDLIBS += \
"$$ARMGCC_INSTALL_PATH"/arm-none-eabi/lib/libm.a "$$ARMGCC_INSTALL_PATH"/arm-none-eabi/lib/libm.a

80
host/lib/usrp/b200/b200_iface.cpp
View File

@ -57,15 +57,11 @@ const static boost::uint8_t B200_VREQ_GET_FPGA_HASH = 0x1D;
const static boost::uint8_t B200_VREQ_SET_FW_HASH = 0x1E; const static boost::uint8_t B200_VREQ_SET_FW_HASH = 0x1E;
const static boost::uint8_t B200_VREQ_GET_FW_HASH = 0x1F; const static boost::uint8_t B200_VREQ_GET_FW_HASH = 0x1F;
const static boost::uint8_t B200_VREQ_LOOP = 0x22; const static boost::uint8_t B200_VREQ_LOOP = 0x22;
const static boost::uint8_t B200_VREQ_SPI_WRITE = 0x32;
const static boost::uint8_t B200_VREQ_SPI_READ = 0x42;
const static boost::uint8_t B200_VREQ_FPGA_CONFIG = 0x55; const static boost::uint8_t B200_VREQ_FPGA_CONFIG = 0x55;
const static boost::uint8_t B200_VREQ_FPGA_RESET = 0x62; const static boost::uint8_t B200_VREQ_FPGA_RESET = 0x62;
const static boost::uint8_t B200_VREQ_GPIF_RESET = 0x72; const static boost::uint8_t B200_VREQ_GPIF_RESET = 0x72;
const static boost::uint8_t B200_VREQ_GET_USB = 0x80; const static boost::uint8_t B200_VREQ_GET_USB = 0x80;
const static boost::uint8_t B200_VREQ_GET_STATUS = 0x83; const static boost::uint8_t B200_VREQ_GET_STATUS = 0x83;
const static boost::uint8_t B200_VREQ_AD9361_CTRL_WRITE = 0x90;
const static boost::uint8_t B200_VREQ_AD9361_CTRL_READ = 0x91;
const static boost::uint8_t B200_VREQ_FX3_RESET = 0x99; const static boost::uint8_t B200_VREQ_FX3_RESET = 0x99;
const static boost::uint8_t B200_VREQ_EEPROM_WRITE = 0xBA; const static boost::uint8_t B200_VREQ_EEPROM_WRITE = 0xBA;
const static boost::uint8_t B200_VREQ_EEPROM_READ = 0xBB; const static boost::uint8_t B200_VREQ_EEPROM_READ = 0xBB;
@ -270,82 +266,6 @@ public:
return recv_bytes; return recv_bytes;
} }
void transact_spi(
unsigned char *tx_data,
size_t num_tx_bits,
unsigned char *rx_data,
size_t num_rx_bits) {
int ret = 0;
boost::uint16_t tx_length = num_tx_bits / 8;
if(tx_data[0] & 0x80) {
ret = fx3_control_write(B200_VREQ_SPI_WRITE, 0x00, \
0x00, tx_data, tx_length);
} else {
ret = fx3_control_write(B200_VREQ_SPI_READ, 0x00, \
0x00, tx_data, tx_length);
}
if (ret < 0)
throw uhd::io_error((boost::format("Failed to write SPI (%d: %s)") % ret % libusb_error_name(ret)).str());
else if (ret != tx_length)
throw uhd::io_error((boost::format("Short write on write SPI (expecting: %d, returned: %d)") % tx_length % ret).str());
if(num_rx_bits) {
boost::uint16_t total_length = num_rx_bits / 8;
ret = fx3_control_read(B200_VREQ_LOOP, 0x00, \
0x00, rx_data, total_length);
if (ret < 0)
throw uhd::io_error((boost::format("Failed to readback (%d: %s)") % ret % libusb_error_name(ret)).str());
else if (ret != total_length)
throw uhd::io_error((boost::format("Short read on readback (expecting: %d, returned: %d)") % total_length % ret).str());
}
}
void ad9361_transact(const unsigned char in_buff[AD9361_DISPATCH_PACKET_SIZE], unsigned char out_buff[AD9361_DISPATCH_PACKET_SIZE]) {
const int bytes_to_write = AD9361_DISPATCH_PACKET_SIZE;
const int bytes_to_read = AD9361_DISPATCH_PACKET_SIZE;
const size_t read_retries = 5;
int ret = fx3_control_write(B200_VREQ_AD9361_CTRL_WRITE, 0x00, 0x00, (unsigned char *)in_buff, bytes_to_write);
if (ret < 0)
throw uhd::io_error((boost::format("Failed to write AD9361 (%d: %s)") % ret % libusb_error_name(ret)).str());
else if (ret != bytes_to_write)
throw uhd::io_error((boost::format("Short write on write AD9361 (expecting: %d, returned: %d)") % bytes_to_write % ret).str());
for (size_t i = 0; i < read_retries; i++)
{
ret = fx3_control_read(B200_VREQ_AD9361_CTRL_READ, 0x00, 0x00, out_buff, bytes_to_read, 3000);
if (ret < 0)
{
if (ret == LIBUSB_ERROR_TIMEOUT)
{
UHD_LOG << (boost::format("Failed to read AD9361 (%d: %s). Retrying (%d of %d)...")
% ret
% libusb_error_name(ret)
% (i+1)
% read_retries
) << std::endl;
}
else
{
throw uhd::io_error((boost::format("Failed to read AD9361 (%d: %s)")
% ret
% libusb_error_name(ret)
).str());
}
}
if (ret == bytes_to_read)
return;
}
throw uhd::io_error(str(boost::format("Failed to read complete AD9361 (expecting: %d, last read: %d)") % bytes_to_read % ret));
}
void load_firmware(const std::string filestring, UHD_UNUSED(bool force) = false) void load_firmware(const std::string filestring, UHD_UNUSED(bool force) = false)
{ {
const char *filename = filestring.c_str(); const char *filename = filestring.c_str();

4
host/lib/usrp/b200/b200_iface.hpp
View File

@ -70,10 +70,6 @@ public:
//! load an FPGA image //! load an FPGA image
virtual boost::uint32_t load_fpga(const std::string filestring) = 0; virtual boost::uint32_t load_fpga(const std::string filestring) = 0;
//! send SPI through the FX3
virtual void transact_spi( unsigned char *tx_data, size_t num_tx_bits, \
unsigned char *rx_data, size_t num_rx_bits) = 0;
virtual void write_eeprom(boost::uint16_t addr, boost::uint16_t offset, const uhd::byte_vector_t &bytes) = 0; virtual void write_eeprom(boost::uint16_t addr, boost::uint16_t offset, const uhd::byte_vector_t &bytes) = 0;
virtual uhd::byte_vector_t read_eeprom(boost::uint16_t addr, boost::uint16_t offset, size_t num_bytes) = 0; virtual uhd::byte_vector_t read_eeprom(boost::uint16_t addr, boost::uint16_t offset, size_t num_bytes) = 0;

2
host/lib/usrp/b200/b200_impl.hpp
View File

@ -45,7 +45,7 @@
#include <uhd/transport/bounded_buffer.hpp> #include <uhd/transport/bounded_buffer.hpp>
#include <boost/weak_ptr.hpp> #include <boost/weak_ptr.hpp>
#include "recv_packet_demuxer_3000.hpp" #include "recv_packet_demuxer_3000.hpp"
static const boost::uint8_t B200_FW_COMPAT_NUM_MAJOR = 0x05; static const boost::uint8_t B200_FW_COMPAT_NUM_MAJOR = 0x06;
static const boost::uint8_t B200_FW_COMPAT_NUM_MINOR = 0x00; static const boost::uint8_t B200_FW_COMPAT_NUM_MINOR = 0x00;
static const boost::uint16_t B200_FPGA_COMPAT_NUM = 0x04; static const boost::uint16_t B200_FPGA_COMPAT_NUM = 0x04;
static const double B200_BUS_CLOCK_RATE = 100e6; static const double B200_BUS_CLOCK_RATE = 100e6;