docs: Moved FPGA manual content to host/docs

- All FPGA manual content is now side-by-side with other manual content.
- Switched instantiating files to using the \subpage command.
- Repaired broken ToC entries.
- Removed references to former FPGA doc directory from cmakelist.

fpga/docs/Makefile

@@ -1,13 +0,0 @@
-#
-# Copyright 2015 Ettus Research LLC
-#
-
-manual:
-	doxygen Doxyfile
-
-clean:
-	@rm -rf html
-	@rm -rf latex
-	@rm -rf *.db
-
-.PHONY: manual clean

fpga/docs/usrp2/build_instructions.md

@@ -1,55 +0,0 @@
-# Generation 2 USRP Build Documentation
-
-## Dependencies and Requirements
-
-### Dependencies
-
-The USRP FPGA build system requires a UNIX-like environment with the following dependencies
-
-- [Xilinx ISE 12.2](http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools/v12_2.html)
-- [GNU Make](https://www.gnu.org/software/make/)
-- (Recommended) [GNU Bash](https://www.gnu.org/software/bash/)
-
-The N200 will work with the WebPack version of ISE.
-
-### Requirements
-
-- [Xilinx ISE Platform Requirements](http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/irn.pdf)
-
-### What FPGA does my USRP have?
-
-- USRP N200: Spartan® 3A-DSP 1800
-- USRP N210: Spartan® 3A-DSP 3400
-
-## Build Instructions
-
-- Download and install [Xilinx ISE 12.2](http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools/v12_2.html)
-
-- To add xtclsh to the PATH and to setup up the Xilinx build environment run
-  + `source <install_dir>/Xilinx/12.2/ISE_DS/settings64.sh` (64-bit platform)
-  + `source <install_dir>/Xilinx/12.2/ISE_DS/settings32.sh` (32-bit platform)
-
-- Navigate to `usrp2/top/{project}` where project is:
-  + N2x0: For USRP N200 and USRP N210
-
-- To build a binary configuration bitstream run `make <target>`
-  where the target is specific to each product. To get a list of supported targets run
-  `make help`.
-
-- The build output will be specific to the product and will be located in the
-  `usrp2/top/{project}/build` directory. Run `make help` for more information.
-
-### N2x0 Targets and Outputs
-
-#### Supported Targets
-- N200R3:  Builds the USRP N200 Rev 3 design.
-- N200R4:  Builds the USRP N200 Rev 4 design.
-- N210R3:  Builds the USRP N210 Rev 3 design.
-- N210R4:  Builds the USRP N210 Rev 4 design.
-
-#### Outputs
-- `build-<target>/u2plus.bit` : Configuration bitstream with header
-- `build-<target>/u2plus.bin` : Configuration bitstream without header
-- `build-<target>/u2plus.syr` : Xilinx system report
-- `build-<target>/u2plus.twr` : Xilinx timing report
-

fpga/docs/usrp2/customize_signal_chain.md

@@ -1,49 +0,0 @@
-# Customizing the Signal Chain in Generation 2 products
-
-## Adding DSP logic to Generation 2 products
-
-As part of the USRP FPGA build-framework, there are several convenient places
-for users to insert custom DSP modules into the transmit and receive chains.
-
-- Before the DDC module
-- After the DDC module
-- Replace the DDC module
-- Before the DUC module
-- After the DUC module
-- Replace the DUC module
-- As an RX packet engine
-- As an TX packet engine
-
-### Customizing the top level makefile
-
-Each USRP device has a makefile associated with it. This makefile contains all
-of the necessary build rules. When making a customized FPGA design, start by
-copying the current makefile for your device. Makefiles can be found in
-`usrp2/top/{product}/Makefile`
-
-Edit your new makefile:
-- Set BUILD_DIR to a unique directory name
-- Set CUSTOM_SRCS for your verilog sources
-- Set CUSTOM_DEFS (see section below)
-
-### Inserting custom modules
-
-CUSTOM_DEFS is a string of space-separate key-value pairs. Set the CUSTOM_DEFS
-variable so the FPGA fabric glue will substitute your custom modules into the
-DSP chain.
-
-Example:
-
-    CUSTOM_DEFS = "TX_ENG0_MODULE=my_tx_engine RX_ENG0_MODULE=my_rx_engine"
-
-Where `my_tx_engine` and `my_rx_engine` are the names of custom verilog modules.
-
-The following module definition keys are possible (X is a DSP number):
-
-- `TX_ENG<X>_MODULE`: Set the module for the transmit chain engine.
-- `RX_ENG<X>_MODULE`: Set the module for the receive chain engine.
-- `RX_DSP<X>_MODULE`: Set the module for the transmit dsp chain.
-- `TX_DSP<X>_MODULE`: Set the module for the receive dsp chain.
-
-Examples of custom modules can be found in the Verilog files in `usrp2/custom/`.
-

fpga/docs/usrp3/simulation.md

@@ -1,16 +0,0 @@
-# Simulation
-
-## Instructions
-
- - \subpage md_usrp3_sim_running_testbenches "Running a Testbench"
- - \subpage md_usrp3_sim_writing_testbenches "Writing a Testbench"
-
-## Library Reference
-
- - \subpage md_usrp3_sim_simulation_libraries "Testbench Simulation Libraries"
-
-## Legacy Library Reference
-
- - \subpage md_usrp3_sim_legacy_testbenches "Legacy Testbenches"
- - \subpage md_usrp3_sim_libs_general "Legacy General Purpose Simulation Libraries"
- - \subpage md_usrp3_sim_libs_axi "Legacy AXI Interface Libraries"

host/docs/06_fpga.md

@@ -1,41 +1,39 @@
-FPGA Manual
-===========
+\page page_fpga FPGA Manual
+
 
 Welcome to the USRP FPGA HDL source code tree! This repository contains
 free & open-source FPGA HDL for the Universal Software Radio Peripheral
 (USRP™) SDR platform, created and sold by Ettus Research. A large
 percentage of the source code is written in Verilog.
 
-## Product Generations
+# Product Generations
 
 This repository contains the FPGA source for the following generations of
 USRP devices.
 
-### Generation 1
+## Generation 1
 
-\li Directory: __usrp1__
+\li Directory: __fpga/usrp1__
 \li Devices: USRP Classic Only
 \li Tools: Quartus from Altera
-\li \subpage md_usrp1_build_instructions "Build Instructions"
+\li \subpage gen1_fpga_build "Build Instructions"
 
 
-### Generation 2
+## Generation 2
 
-\li Directory: __usrp2__
+\li Directory: __fpga/usrp2__
 \li Devices: USRP N2X0, USRP B100, USRP E1X0, USRP2
 \li Tools: ISE from Xilinx, GNU make
-\li \subpage md_usrp2_build_instructions "Build Instructions"
-\li \subpage md_usrp2_customize_signal_chain "Customization Instructions"
+\li \subpage gen2_fpga_build "Build and Customization Instructions"
 
-### Generation 3
+## Generation 3
 
-\li Directory: __usrp3__
+\li Directory: __fpga/usrp3__
 \li Devices: USRP B2XX, USRP E3XX, USRP N3XX, USRP X3XX, USRP X4XX
 \li Tools: Vivado/ISE from Xilinx, GNU make
-\li \subpage md_usrp3_build_instructions "Build Instructions"
-\li \subpage md_usrp3_simulation "Simulation Instructions"
+\li \subpage gen3_fpga_build_sim "Generation 3 USRP Build Documentation"
 
-## Pre-built FPGA Images
+# Pre-built FPGA Images
 
 Pre-built FPGA and Firmware images are not hosted here. Please visit \ref page_images
 for instructions on downloading and using pre-built images. In most cases, running

host/docs/CMakeLists.txt

@@ -22,16 +22,11 @@ set(ENABLE_MANUAL_OR_DOXYGEN false)
 LIBUHD_REGISTER_COMPONENT("Manual" ENABLE_MANUAL ON "DOXYGEN_FOUND" OFF OFF)
 
 if(ENABLE_MANUAL)
-    set(FPGA_SOURCE_DIR "${UHD_SOURCE_DIR}/../fpga")
     set(ENABLE_MANUAL_OR_DOXYGEN true)
     file(GLOB manual_sources "*.dox")
-    file(GLOB_RECURSE fpga_manual_sources "${FPGA_SOURCE_DIR}/docs/*.md")
-    list(APPEND manual_sources ${fpga_manual_sources})
     set(DOXYGEN_DEPENDENCIES ${manual_sources})
-    set(DOXYGEN_INPUT_DIRS "${UHD_SOURCE_DIR}/docs ${CMAKE_CURRENT_BINARY_DIR} ${FPGA_SOURCE_DIR}/docs")
+    set(DOXYGEN_INPUT_DIRS "${UHD_SOURCE_DIR}/docs ${CMAKE_CURRENT_BINARY_DIR}")
     set(DOXYGEN_DEP_COMPONENT "manual")
-    set(DOXYGEN_FPGA_MANUAL_REFERENCE "\\subpage md_fpga \"Part III: FPGA Manual\"")
-    set(DOXYGEN_STRIP_EXTRA "${UHD_SOURCE_DIR}/../fpga/docs")
     set(DOXYGEN_EXCLUDE_DIRS "")
 endif(ENABLE_MANUAL)
 

host/docs/devices/usrp_b200.dox

@@ -123,7 +123,7 @@ images:
 The FPGA image is provided in source code and can thus be modified and rebuilt
 to serve custom purposes. For example, additional filtering or other DSP
 operations can be inserted into the FPGA before or after the DAC or ADC stages,
-respectively. Refer to the \ref md_fpga "FPGA Manual" for further information on
+respectively. Refer to the \ref page_fpga "FPGA Manual" for further information on
 how to rebuild the FPGA.
 
 To control user-defined IP, the `USER_SETTINGS` parameter for the `radio_legacy`

host/docs/driver_usage/images.dox

@@ -81,7 +81,7 @@ The build commands for a particular image can be found in
 USRP Xilinx FPGA images are built with either Vivado or one of two versions of ISE,
 depending on the device.
 
-Refer to the \ref md_fpga "FPGA Manual" for setup and build instructions
+Refer to the \ref page_fpga "FPGA Manual" for setup and build instructions
 relevant to your device family.
 
 \subsection images_building_zpu ZPU firmware builds

host/docs/fpga/usrp1/usrp1_build_instructions.md

@@ -1,4 +1,4 @@
-# Generation 1 USRP Build Documentation
+\page gen1_fpga_build Generation 1 USRP Build Documentation
 
 The USRP FPGA build system requires only the Altera FPGA tools
 

host/docs/fpga/usrp2/build_instructions.md

@@ -0,0 +1,102 @@
+\page gen2_fpga_build Generation 2 USRP Build Documentation
+
+# Dependencies and Requirements
+
+## Dependencies
+
+The USRP FPGA build system requires a UNIX-like environment with the following dependencies
+
+- [Xilinx ISE 12.2](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html)
+- [GNU Make](https://www.gnu.org/software/make/)
+- (Recommended) [GNU Bash](https://www.gnu.org/software/bash/)
+
+The N200 will work with the WebPack version of ISE.
+
+## Requirements
+
+- [Xilinx ISE Platform Requirements](http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/irn.pdf)
+
+## What FPGA does my USRP have?
+
+- USRP N200: Spartan® 3A-DSP 1800
+- USRP N210: Spartan® 3A-DSP 3400
+
+# Build Instructions
+
+- Download and install [Xilinx ISE 12.2](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html)
+
+- To add xtclsh to the PATH and to setup up the Xilinx build environment run
+  + `source <install_dir>/Xilinx/12.2/ISE_DS/settings64.sh` (64-bit platform)
+  + `source <install_dir>/Xilinx/12.2/ISE_DS/settings32.sh` (32-bit platform)
+
+- Navigate to `usrp2/top/{project}` where project is:
+  + N2x0: For USRP N200 and USRP N210
+
+- To build a binary configuration bitstream run `make <target>`
+  where the target is specific to each product. To get a list of supported targets run
+  `make help`.
+
+- The build output will be specific to the product and will be located in the
+  `usrp2/top/{project}/build` directory. Run `make help` for more information.
+
+## N2x0 Targets and Outputs
+
+### Supported Targets
+- N200R3:  Builds the USRP N200 Rev 3 design.
+- N200R4:  Builds the USRP N200 Rev 4 design.
+- N210R3:  Builds the USRP N210 Rev 3 design.
+- N210R4:  Builds the USRP N210 Rev 4 design.
+
+### Outputs
+- `build-<target>/u2plus.bit` : Configuration bitstream with header
+- `build-<target>/u2plus.bin` : Configuration bitstream without header
+- `build-<target>/u2plus.syr` : Xilinx system report
+- `build-<target>/u2plus.twr` : Xilinx timing report
+
+# Adding DSP logic to Generation 2 products
+
+As part of the USRP FPGA build-framework, there are several convenient places
+for users to insert custom DSP modules into the transmit and receive chains.
+
+- Before the DDC module
+- After the DDC module
+- Replace the DDC module
+- Before the DUC module
+- After the DUC module
+- Replace the DUC module
+- As an RX packet engine
+- As an TX packet engine
+
+## Customizing the top level makefile
+
+Each USRP device has a makefile associated with it. This makefile contains all
+of the necessary build rules. When making a customized FPGA design, start by
+copying the current makefile for your device. Makefiles can be found in
+`usrp2/top/{product}/Makefile`
+
+Edit your new makefile:
+- Set BUILD_DIR to a unique directory name
+- Set CUSTOM_SRCS for your verilog sources
+- Set CUSTOM_DEFS (see section below)
+
+## Inserting custom modules
+
+CUSTOM_DEFS is a string of space-separate key-value pairs. Set the CUSTOM_DEFS
+variable so the FPGA fabric glue will substitute your custom modules into the
+DSP chain.
+
+Example:
+
+    CUSTOM_DEFS = "TX_ENG0_MODULE=my_tx_engine RX_ENG0_MODULE=my_rx_engine"
+
+Where `my_tx_engine` and `my_rx_engine` are the names of custom verilog modules.
+
+The following module definition keys are possible (X is a DSP number):
+
+- `TX_ENG<X>_MODULE`: Set the module for the transmit chain engine.
+- `RX_ENG<X>_MODULE`: Set the module for the receive chain engine.
+- `RX_DSP<X>_MODULE`: Set the module for the transmit dsp chain.
+- `TX_DSP<X>_MODULE`: Set the module for the receive dsp chain.
+
+Examples of custom modules can be found in the Verilog files in `usrp2/custom/`.
+

host/docs/fpga/usrp3/build_instructions.md

@@ -1,12 +1,12 @@
-# Generation 3 USRP Build Documentation
+\page gen3_fpga_build Build Documentation
 
-## Dependencies and Requirements
+# Dependencies and Requirements
 
-### Dependencies
+## Dependencies
 
 The USRP FPGA build system requires a UNIX-like environment with the following dependencies:
 
-- [Xilinx Vivado ML Enterprise 2021.1](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2021-1.html) (For 7 Series and SoCs)
+- [Xilinx Vivado ML Enterprise 2021.1](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html) (For 7 Series and SoCs)
   + [AR76780 Patch for Vivado 2021.1](https://support.xilinx.com/s/article/76780?language=en_US)
 - [Xilinx ISE Design Suite 14.7](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html) (For all other FPGAs)
 - [GNU Make 3.6+](https://www.gnu.org/software/make/)
@@ -20,7 +20,7 @@ the full licensed versions:
 - USRP B200/B200mini (ISE WebPACK)
 - USRP E310/E312/E313 (Vivado ML Standard)
 
-### System Requirements
+## System Requirements
 
 In general, a high-performance PC with a lot of disk space and memory is
 recommended for building FPGA images. For USRP FPGA builds, the following
@@ -37,9 +37,9 @@ For other system requirements related to the Xilinx tools, see the appropriate
 Xilinx documentation for the build tool required by your FPGA type.
 
 - [Xilinx Vivado Release Notes](https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2021_1/ug973-vivado-release-notes-install-license.pdf)
-- [Xilinx ISE Platform Requirements](http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/irn.pdf)
+- [Xilinx ISE Platform Requirements](https://docs.amd.com/v/u/en-US/irn)
 
-### What FPGA does my USRP have?
+## What FPGA does my USRP have?
 
 | USRP           | FPGA                                          | Design Tool       |
 | -------------- | --------------------------------------------- | ----------------- |
@@ -58,9 +58,9 @@ Xilinx documentation for the build tool required by your FPGA type.
 
 Note: The Xilinx installation must include support for the specified FPGA family. You can save disk space and installation time by only installing support for the FPGAs you intend to use.
 
-## Build Environment Setup
+# Build Environment Setup
 
-### Download and Install Xilinx Tools
+## Download and Install Xilinx Tools
 
 Download and install Xilinx Vivado or Xilinx ISE based on the target USRP.
 - The recommended installation directory is `/opt/Xilinx/` for Linux and `C:\Xilinx` in Windows.
@@ -68,7 +68,7 @@ Download and install Xilinx Vivado or Xilinx ISE based on the target USRP.
 - You may need to acquire a synthesis and implementation license from Xilinx to build some USRP designs.
 - You may need to acquire a simulation license from Xilinx to run some testbenches.
 
-### Download and Install ModelSim (Optional)
+## Download and Install ModelSim (Optional)
 
 If you prefer to use ModelSim, download and install Mentor ModelSim using the
 link above.
@@ -76,7 +76,7 @@ link above.
 - Supported versions are PE, DE, SE, DE-64 and SE-64
 - You may need to acquire a license from Mentor Graphics to run ModelSim
 
-### Setting up build dependencies on Ubuntu and Fedora
+## Setting up build dependencies on Ubuntu and Fedora
 
 For building any RFNoC-capable device (out of the list above, that is all devices
 except for the B200 series USRPs), the `rfnoc_image_builder` utility must be
@@ -94,7 +94,7 @@ To only install dependencies for building B200 images, use the package manager:
 
 Your actual command may differ.
 
-### Setting up build dependencies on Windows (using Cygwin)
+## Setting up build dependencies on Windows (using Cygwin)
 
 **NOTE**: Windows is only supported with Vivado. The build system does not support Xilinx ISE in Windows.
 
@@ -104,12 +104,12 @@ The following additional packages are also required and can be selected in the G
 
     python3 patch patchutils bash make gcc-core doxygen
 
-## Build Instructions (Xilinx Vivado only)
+# Build Instructions (Xilinx Vivado only)
 
 **Important**: Starting with UHD 4.7, all RFNoC capable targets must be built
 using `rfnoc_image_builder`, which is installed as part of UHD.
 
-### Makefile based Builder
+## Makefile based Builder
 
 - Navigate to `<repo>/fpga/usrp3/top/{project}` where `{project}` is:
   + `x300`: For USRP X300 and USRP X310
@@ -142,15 +142,15 @@ Notes:
 
   first, before calling make.
 
-### Environment Utilities
+## Environment Utilities
 
 The build environment also defines many ease-of-use utilities. Please use
-the \subpage md_usrp3_vivado_env_utils "Vivado Utility Reference" page for
+the \ref gen3_vivado_env_utils "Vivado Utility Reference" page for
 a list and usage information.
 
-### Known Issues
+## Known Issues
 
-#### N2rt13HDRTExceptionE in Vivado 2021.1
+### N2rt13HDRTExceptionE in Vivado 2021.1
 
 **Problem:**
 
@@ -167,7 +167,7 @@ Use a different Git hash or make a non-functional source code change to the HDL
 
 According to [Xilinx Support](https://support.xilinx.com/s/question/0D52E00006zHvfcSAC/router-crashes-after-a-second-routedesign-call?language=en_US), this issue will be fixed in a future version of Vivado.
 
-#### Error During cs_server Initialization in Vivado 2021.1
+### Error During cs_server Initialization in Vivado 2021.1
 
 **Problem:**
 
@@ -187,9 +187,9 @@ to connect to the hardware:
 
     set_param labtools.override_cs_server_version_check 1
 
-## Build Instructions (Xilinx ISE only, for B200 series)
+# Build Instructions (Xilinx ISE only, for B200 series)
 
-### Makefile Based Builder
+## Makefile Based Builder
 
 - To add xtclsh to the PATH and to setup up the Xilinx build environment run
   + `source <install_dir>/Xilinx/14.7/ISE_DS/settings64.sh` (64-bit platform)
@@ -206,35 +206,35 @@ to connect to the hardware:
 - The build output will be specific to the product and will be located in the
   `<repo>/fpga/usrp3/top/{project}/build` directory. Run `make help` for more information.
 
-## Targets and Outputs
+# Targets and Outputs
 
-### B2x0 Targets and Outputs
+## B2x0 Targets and Outputs
 
-#### Supported Targets
+### Supported Targets
 - B200:  Builds the USRP B200 design.
 - B210:  Builds the USRP B210 design.
 
-#### Outputs
+### Outputs
 - `build/usrp_<product>_fpga.bit` : Configuration bitstream with header
 - `build/usrp_<product>_fpga.bin` : Configuration bitstream without header
 - `build/usrp_<product>_fpga.syr` : Xilinx system report
 - `build/usrp_<product>_fpga.twr` : Xilinx timing report
 
-### B2xx-mini Targets and Outputs
+## B2xx-mini Targets and Outputs
 
-#### Supported Targets
+### Supported Targets
 - B200mini:  Builds the USRP B200-mini design.
 - B205mini:  Builds the USRP B205-mini design.
 
-#### Outputs
+### Outputs
 - `build/usrp_<product>_fpga.bit` : Configuration bitstream with header
 - `build/usrp_<product>_fpga.bin` : Configuration bitstream without header
 - `build/usrp_<product>_fpga.syr` : Xilinx system report
 - `build/usrp_<product>_fpga.twr` : Xilinx timing report
 
-### X3x0 Targets and Outputs
+## X3x0 Targets and Outputs
 
-#### Supported Targets
+### Supported Targets
 
 Use `make help` to produce a list of valid targets, as well as how to build them
 using `rfnoc_image_builder`.
@@ -250,15 +250,15 @@ using `rfnoc_image_builder`.
 - X310_XA:  USRP X310. 10GigE on SFP+ Port0, Aurora on SFP+ Port1.
 - X300_XA:  USRP X300. 10GigE on SFP+ Port0, Aurora on SFP+ Port1.
 
-#### Outputs
+### Outputs
 - `build/usrp_<product>_fpga_<image_type>.bit` :    Configuration bitstream with header
 - `build/usrp_<product>_fpga_<image_type>.bin` :    Configuration bitstream without header
 - `build/usrp_<product>_fpga_<image_type>.lvbitx` : Configuration bitstream for PCIe (NI-RIO)
 - `build/usrp_<product>_fpga_<image_type>.rpt` :    System, utilization and timing summary report
 
-### E310 Targets and Outputs
+## E310 Targets and Outputs
 
-#### Supported Targets
+### Supported Targets
 
 Use `make help` to produce a list of valid targets, as well as how to build them
 using `rfnoc_image_builder`.
@@ -268,14 +268,14 @@ using `rfnoc_image_builder`.
 - E310_SG1_IDLE:  Builds the USRP E310 idle design (speed grade 1).
 - E310_SG3_IDLE:  Builds the USRP E310 idle design (speed grade 3).
 
-#### Outputs
+### Outputs
 - `build/usrp_<product>_fpga.bit` : Configuration bitstream with header
 - `build/usrp_<product>_fpga.dts` : Device tree overlay
 - `build/usrp_<product>_fpga.rpt` : System, utilization and timing summary report
 
-### E320 Targets and Outputs
+## E320 Targets and Outputs
 
-#### Supported Targets
+### Supported Targets
 Use `make help` to produce a list of valid targets, as well as how to build them
 using `rfnoc_image_builder`.
 
@@ -283,14 +283,14 @@ using `rfnoc_image_builder`.
 - E320_XG: 10GigE on SFP+ Port.
 - E320_AA: Aurora on SFP+ Port.
 
-#### Outputs
+### Outputs
 - `build/usrp_<product>_fpga.bit` : Configuration bitstream with header
 - `build/usrp_<product>_fpga.dts` : Device tree overlay
 - `build/usrp_<product>_fpga.rpt` : System, utilization and timing summary report
 
-### N3xx Targets and Outputs
+## N3xx Targets and Outputs
 
-#### Supported Targets
+### Supported Targets
 
 The targets depend on the actual hardware the FPGA image is being deployed to.
 Unlike the X300 Series, the daughterboards are an integral part of the module
@@ -321,14 +321,14 @@ using `rfnoc_image_builder`.
 
 For the N320 targets see also the N320 manual page on the UHD manual.
 
-#### Outputs
+### Outputs
 - `build/usrp_<product>_fpga.bit` : Configuration bitstream with header
 - `build/usrp_<product>_fpga.dts` : Device tree overlay
 - `build/usrp_<product>_fpga.rpt` : System, utilization and timing summary report
 
-### X4x0 Targets and Outputs
+## X4x0 Targets and Outputs
 
-#### Supported Targets
+### Supported Targets
 
 Unlike other USRPs, the target types do not only describe the connector
 configuration, but also the available master clock rates. For example, the FPGA
@@ -344,12 +344,12 @@ Run `make help` in the `<repo>/fpga/usrp3/top/x400/` directory to see
 the complete list of options available. It will list targets for both X410 and
 X440.
 
-#### Outputs
+### Outputs
 - `build/usrp_<product>_fpga.bit` : Configuration bitstream with header
 - `build/usrp_<product>_fpga.dts` : Device tree overlay
 - `build/usrp_<product>_fpga.rpt` : System, utilization and timing summary report
 
-### Additional Build Options
+## Additional Build Options
 
 It is possible to make a target and specify additional options in the form `VAR=VALUE` in
 the command. For example:
@@ -358,14 +358,14 @@ the command. For example:
 
 The options available are described in the following subsections.
 
-#### Xilinx Vivado Make Options
+### Xilinx Vivado Make Options
 
 - `GUI=1` : Run the Vivado build in GUI mode instead of batch mode. After the build is complete, Vivado provides an option to save the fully configured project for customization
 - `CHECK=1` : Run elaboration only to check HDL syntax
 - `SYNTH=1` : Run synthesis only
 - `TOP=<module>` : Specify an alternate top-level module for syntax checking
 
-#### Xilinx ISE Make Options
+### Xilinx ISE Make Options
 
 - `PROJECT_ONLY=1` : Only create a Xilinx project for the specified target(s). Useful for use with the ISE GUI.
-- `EXPORT_ONLY=1` :  Export build targets from a GUI build to the build directory. Requires the project in build-\*_\* to be built.
+- `EXPORT_ONLY=1` :  Export build targets from a GUI build to the build directory. Requires the project in build-\*_\* to be built.

host/docs/fpga/usrp3/sim/legacy_testbenches.md

@@ -1,4 +1,4 @@
-# Legacy Testbenches
+\page usrp3_sim_legacy_testbenches Legacy Testbenches
 
 Some existing testbenches use the following testbench style and infrastructure.
 This documentation is from UHD 3.x but is included here due to its continued
@@ -97,7 +97,7 @@ Below is a sample legacy SystemVerilog testbench.
 
 Each testbench should have the following basic components:
 
-## Timescale Defines and Includes
+# Timescale Defines and Includes
 
     `timescale 1ns/1ps
     `define NS_PER_TICK     1
@@ -113,7 +113,7 @@ nanoseconds per simulator tick. This can be a floating point number.
 
 In addition to the timescale, you may include any Verilog/SystemVerilog headers here.
 
-## Main Module Definition
+# Main Module Definition
 
     `include "sim_exec_report.vh"
 
@@ -158,7 +158,7 @@ For the sake of convention it should be called ``tb_main``. *All test cases must
 have other initial block but they must not call macros from ``sim_exec_report.vh`` because the code
 there is not thread-safe.
 
-## Test Cases
+# Test Cases
 
 A test case in this context is defined as an independent entity that validates an aspect of the DUT behavior
 and which is independent from other test cases i.e. the result of one test case should ideally not affect others.

host/docs/fpga/usrp3/sim/libs_axi.md

@@ -1,14 +1,14 @@
-# Legacy AXI Interface Libraries
+\page usrp3_sim_libs_axi Legacy AXI Interface Libraries
 
 This document describes legacy AXI interface libraries used by some
 testbenches. They are included here due to their continued use.
 
-## AXI4 Stream (sim\_axis\_lib.vh)
+# AXI4 Stream (sim\_axis\_lib.svh)
 
 Defines ``axis_t``, an AXI Stream bus interface that implements several tasks to send and 
 receive data on the bus.
 
-### Definition
+## Definition
 
     interface axis_t #(parameter DWIDTH = 64)
                       (input clk);
@@ -21,20 +21,20 @@ receive data on the bus.
     modport slave (input tdata, input tvalid, input tlast, output tready);
 
 
-### Operations
+## Operations
 
-#### push\_word
+### push\_word
 
     // Push a word onto the AXI-Stream bus and wait for it to transfer
     // Args:
     // - word: The data to push onto the bus
     // - eop (optional): End of packet (asserts tlast)
 
-#### push\_bubble
+### push\_bubble
 
     // Push a bubble cycle onto the AXI-Stream bus
 
-#### pull\_word
+### pull\_word
 
     // Wait for a sample to be transferred on the AXI Stream
     // bus and return the data and last
@@ -42,21 +42,21 @@ receive data on the bus.
     // - word: The data pulled from the bus
     // - eop: End of packet (tlast)
 
-#### wait\_for\_bubble
+### wait\_for\_bubble
 
     // Wait for a bubble cycle on the AXI Stream bus
 
-#### wait\_for\_pkt
+### wait\_for\_pkt
 
     // Wait for a packet to finish on the bus
 
-#### push\_rand\_pkt
+### push\_rand\_pkt
 
     // Push a packet with random data onto to the AXI Stream bus
     // Args:
     // - num_samps: Packet size.
 
-#### push\_ramp\_pkt
+### push\_ramp\_pkt
 
     // Push a packet with a ramp on to the AXI Stream bus
     // Args:
@@ -64,15 +64,14 @@ receive data on the bus.
     // - ramp_start: Start value for the ramp
     // - ramp_inc: Increment per clock cycle
 
-## Compressed VITA (sim\_chdr\_lib.vh)
+# Compressed VITA (sim\_cvita\_lib.svh)
 
-Note: This section describes legacy CHDR in 3.x and earlier. As of UHD 4.0,
-the CHDR protocol and format has changed.
+**Note: This section describes legacy CHDR in 3.x and earlier. As of UHD 4.0, the CHDR protocol and format has changed.**
 
 Defines ``cvita_stream_t``, an AXI Stream bus interface that implements the CHDR protocol and 
 several tasks to send and receive data on the bus.
 
-### CHDR
+## CHDR
 
     typedef enum logic [1:0] {
       DATA=2'b00, FC=2'b01, CMD=2'b10, RESP=2'b11
@@ -88,37 +87,37 @@ several tasks to send and receive data on the bus.
       logic [63:0]  timestamp;
     } cvita_hdr_t;
 
-#### Operations
+### Operations
 
  - ``flatten_chdr_no_ts``: Flatten header struct to a 64-bit bus. No timestamp.
  - ``unflatten_chdr_no_ts``: Decode a 64-bit header and populate the ``cvita_hdr_t`` struct. No timestamp.
  - ``unflatten_chdr``: Decode a 64-bit header and populate the ``cvita_hdr_t`` struct. Timestamp supported.
 
-### CVITA Stream Type
+## CVITA Stream Type
 
-#### Definition
+### Definition
 
     interface cvita_stream_t (input clk);
       axis_t #(.DWIDTH(64)) axis (.clk(clk));
 
-#### push\_hdr
+### push\_hdr
 
     // Push a CVITA header into the stream
     // Args:
     // - hdr: The header to push
   
-#### push\_data
+### push\_data
 
     // Push a word onto the AXI-Stream bus and wait for it to transfer
     // Args:
     // - word: The data to push onto the bus
     // - eop: End of packet (asserts tlast)
 
-#### push\_bubble
+### push\_bubble
 
     // Push a bubble cycle on the AXI-Stream bus
 
-#### pull\_word
+### pull\_word
 
     // Wait for a sample to be transferred on the AXI Stream
     // bus and return the data and last
@@ -126,15 +125,15 @@ several tasks to send and receive data on the bus.
     // - word: The data pulled from the bus
     // - eop: End of packet (tlast)
 
-#### wait\_for\_bubble
+### wait\_for\_bubble
 
     // Wait for a bubble cycle on the AXI Stream bus
 
-#### wait\_for\_pkt
+### wait\_for\_pkt
 
     // Wait for a packet to finish on the bus
 
-#### wait\_for\_pkt\_get\_info
+### wait\_for\_pkt\_get\_info
 
     // Wait for a packet to finish on the bus and extract the header and payload statistics.
     
@@ -146,7 +145,7 @@ several tasks to send and receive data on the bus.
       logic [63:0]  crc;
     } cvita_stats_t;
 
-#### push\_rand\_pkt
+### push\_rand\_pkt
 
     // Push a packet with random data onto to the AXI Stream bus
     // Args:
@@ -154,7 +153,7 @@ several tasks to send and receive data on the bus.
     // - hdr: Header to attach to packet (length will be ignored)
     // - timestamp: Optional timestamp
 
-#### push\_ramp\_pkt
+### push\_ramp\_pkt
 
     // Push a packet with a ramp on to the AXI Stream bus
     // Args:
@@ -164,12 +163,12 @@ several tasks to send and receive data on the bus.
     // - hdr: Header to attach to packet (length will be ignored)
     // - timestamp: Optional timestamp
 
-## Memory Mapped AXI4 (sim\_axi4\_lib.vh)
+# Memory Mapped AXI4 (sim\_axi4\_lib.svh)
 
 Defines the following interfaces to group signals in the AXI4 bus.
 WIP: No functions or tasks implemented yet.
 
-#### Address
+## Address
 
     interface axi4_addr_t #(parameter AWIDTH=32, parameter IDWIDTH=4)
                            (input clk);
@@ -193,7 +192,7 @@ WIP: No functions or tasks implemented yet.
     
     endinterface
     
-#### Write Data
+## Write Data
 
     interface axi4_wdata_t #(parameter DWIDTH=64)
                            (input clk);
@@ -210,7 +209,7 @@ WIP: No functions or tasks implemented yet.
     
     endinterface
 
-#### Write Response
+## Write Response
 
     interface axi4_resp_t #(parameter IDWIDTH=4)
                            (input clk);
@@ -226,7 +225,7 @@ WIP: No functions or tasks implemented yet.
     
     endinterface
 
-#### Read Data
+## Read Data
 
     interface axi4_rdata_t #(parameter DWIDTH=64, parameter IDWIDTH=4)
                            (input clk);
@@ -244,7 +243,7 @@ WIP: No functions or tasks implemented yet.
     
     endinterface
 
-#### Meta: AXI4 Writer
+## Meta: AXI4 Writer
 
     interface axi4_wr_t #(parameter DWIDTH=64, parameter AWIDTH=32, parameter IDWIDTH=4)
                          (input clk);
@@ -258,7 +257,7 @@ WIP: No functions or tasks implemented yet.
     
     endinterface
     
-#### Meta: AXI4 Reader
+## Meta: AXI4 Reader
 
     interface axi4_rd_t #(parameter DWIDTH=64, parameter AWIDTH=32, parameter IDWIDTH=4)
                          (input clk);

host/docs/fpga/usrp3/sim/libs_general.md

@@ -1,13 +1,13 @@
-# Legacy Simulation Libraries
+\page usrp3_sim_libs_general Legacy Simulation Libraries
 
 This document describes legacy simulation libraries used by some testbenches.
 They are included here due to their continued use.
 
-## Execution and Reporting (sim\_exec\_report.vh)
+# Execution and Reporting (sim\_exec\_report.vh)
 
 Macros to do boilerplate testbench initialization and utilities to define test cases
 
-#### TEST\_BENCH\_INIT
+## TEST\_BENCH\_INIT
 
     // Initializes state for a test bench.
     // This macro *must be* called within the testbench module but 
@@ -25,7 +25,7 @@ Macros to do boilerplate testbench initialization and utilities to define test c
     //  - ns_per_tick:      The time_unit_base from the timescale declaration
     //
 
-#### TEST\_CASE\_START
+## TEST\_CASE\_START
 
     // Indicates the start of a test case
     // This macro *must be* called inside the primary initial block
@@ -35,7 +35,7 @@ Macros to do boilerplate testbench initialization and utilities to define test c
     //  - test_name:        The name of the test.
     //
 
-#### TEST\_CASE\_DONE
+## TEST\_CASE\_DONE
     // Indicates the end of a test case
     // This macro *must be* called inside the primary initial block
     // The pass/fail status of test case is determined based on the
@@ -47,7 +47,7 @@ Macros to do boilerplate testbench initialization and utilities to define test c
     //  - test_result:  User specified outcome
     //
 
-#### ASSERT\_FATAL
+## ASSERT\_FATAL
 
     // Wrapper around a an assert.
     // ASSERT_FATAL throws an error assertion and halts the simulator
@@ -59,7 +59,7 @@ Macros to do boilerplate testbench initialization and utilities to define test c
     //  - msg:  Message for the assert
     //
 
-#### ASSERT\_ERROR
+## ASSERT\_ERROR
 
     // Wrapper around a an assert.
     // ASSERT_ERROR throws an error assertion and fails the test case
@@ -71,7 +71,7 @@ Macros to do boilerplate testbench initialization and utilities to define test c
     //  - msg:  Message for the assert
     //
 
-#### ASSERT\_WARNING
+## ASSERT\_WARNING
 
     // Wrapper around a an assert.
     // ASSERT_WARNING throws an warning assertion but does not fail the
@@ -83,11 +83,11 @@ Macros to do boilerplate testbench initialization and utilities to define test c
     //  - msg:  Message for the assert
     //
 
-## Clocks and Resets (sim\_clks\_rsts.vh)
+# Clocks and Resets (sim\_clks\_rsts.vh)
 
 Shortcut macros to create typical clock and reset signals.
 
-#### DEFINE\_CLK
+## DEFINE\_CLK
 
     // Generates a persistent clock that starts at t=0 and runs forever
     //
@@ -98,7 +98,7 @@ Shortcut macros to create typical clock and reset signals.
     //  - duty_cycle: Percentage duty cycle
     //
 
-#### DEFINE\_LATE\_START\_CLK
+## DEFINE\_LATE\_START\_CLK
 
     // Generates a clock that starts at the specified time and runs forever
     //
@@ -111,7 +111,7 @@ Shortcut macros to create typical clock and reset signals.
     //  - start_time_res: Start time resolution (must be > timescale increment and < start_time)
     //
 
-#### DEFINE_RESET
+## DEFINE_RESET
 
     // Generates an active high reset
     //
@@ -122,7 +122,7 @@ Shortcut macros to create typical clock and reset signals.
     //  - reset_duration: Duration of reset assertion
     //
 
-#### DEFINE_RESET_N
+## DEFINE_RESET_N
 
     // Generates an active low reset
     //
@@ -133,13 +133,13 @@ Shortcut macros to create typical clock and reset signals.
     //  - reset_duration: Duration of reset assertion
     //
 
-## File I/O (sim\_file\_io.svh)
+# File I/O (sim\_file\_io.svh)
 
-### interface data\_file\_t
+## interface data\_file\_t
 
 Defines a ``data_file_t`` interface with the following functions:
 
-#### open
+### open
 
     // Open the data file for reading or writing.
     //
@@ -148,14 +148,14 @@ Defines a ``data_file_t`` interface with the following functions:
     //  - mode: RW mode (Choose from: READ, WRITE, APPEND)
     //
 
-#### close
+### close
 
     // Close an open data file. No-op if file isn't already open
     //
     // Usage: close()
     //
 
-#### is_eof
+### is_eof
 
     // Is end-of-file reached.
     //
@@ -164,7 +164,7 @@ Defines a ``data_file_t`` interface with the following functions:
     // - eof: A boolean
     //
 
-#### readline
+### readline
 
     // Read a line from the datafile
     //
@@ -173,7 +173,7 @@ Defines a ``data_file_t`` interface with the following functions:
     // - data: A logic array of width DWIDTH containing the read word
     //
 
-#### writeline
+### writeline
 
     // Write a line to the datafile
     //

host/docs/fpga/usrp3/sim/running_testbenches.md

@@ -1,4 +1,4 @@
-# Running a Testbench
+\page usrp3_sim_running_testbenches Running a Testbench
 
 Each executable testbench has its own Makefile that automatically pulls in support
 for all supported simulators. The build infrastructure supports the following simulators:
@@ -23,7 +23,7 @@ all supported simulator targets. Currently, the following targets will work:
     vcom:       Run ModelSim/Questa compiler to compile HDL files
     vclean:     Cleanup ModelSim/Questa intermediate files
 
-## Using Xilinx Vivado XSim
+# Using Xilinx Vivado XSim
 
 XSim is the built-in simulator in the Xilinx Vivado toolchain. If you already met the
 prerequisites for building an FPGA image, then you don't need to install anything else.
@@ -42,9 +42,9 @@ Follow these steps to run a testbench:
   ``$ make xsim``
 
 
-## Using Siemens ModelSim or Questa
+# Using Siemens ModelSim or Questa
 
-### Setting Up ModelSim or QuestaSim
+## Setting Up ModelSim or QuestaSim
 
 ModelSim and Questa are third-party simulation tools that are compatible with
 Vivado and the USRP FPGA build infrastructure.
@@ -91,7 +91,7 @@ Use the following one-time setup to install and configure ModelSim on your syste
   If they have already been built, you can set the ``SIM_COMPLIBDIR``
   environment variable to point to their location and rerun setupenv.sh.
 
-### Simulating with ModelSim through Vivado
+## Simulating with ModelSim through Vivado
 
 Follow these steps to run a testbench using ModelSim with Vivado:
 
@@ -113,7 +113,7 @@ Follow these steps to run a testbench using ModelSim with Vivado:
 
   ``$ make vsim GUI=1``
 
-### Simulating with ModelSim
+## Simulating with ModelSim
 
 To run the simulation using ModelSim natively, the process is the same as
 above, except use the `modelsim` make target.
@@ -140,7 +140,7 @@ ARGS are simply appended to the ModelSim `vsim` command line invocation. LIBS
 are added to the "-L" vsim command line argument. These can also be added to
 the Makefile for the testbench.
 
-### Simulating with QuestaSim
+## Simulating with QuestaSim
 
 For Questa, use the ``qsim`` target instead of ``msim``. For example:
 
@@ -150,7 +150,7 @@ Because the commands for Questa are very similar to ModelSim, you can also use
 the ``msim`` target with Questa, but this will use the classic GUI and the
 legacy +acc mode with vopt. +acc mode is no longer recommended with Questa.
 
-### Compiling the Simulation with ModelSim or Questa
+## Compiling the Simulation with ModelSim or Questa
 
 To compile your code in ModelSim or Questa, without running the simulation,
 use the `vcom` target.
@@ -164,9 +164,9 @@ Using the `msim`/`qsim` and `vcom` targets allows for more rapid simulation
 iterations than when using Vivado.
 
 
-## Troubleshooting
+# Troubleshooting
 
-#### Vivado Not Found
+## Vivado Not Found
 
 If running the setupenv.sh script returns an error like the following:
 
@@ -178,7 +178,7 @@ run the following:
 
 ``$ source <repo>/fpga/usrp3/top/<product>/setupenv.sh --vivado-path=<PATH>``
 
-#### ModelSim/Questa Not Found
+## ModelSim/Questa Not Found
 
 If running the setupenv.sh script returns an error like the following:
 
@@ -201,7 +201,7 @@ in a non-default location, run the following:
 
     $ source <repo>/fpga/usrp3/top/<product>/setupenv.sh --modelsim-path=<PATH>
 
-#### ModelSim Simulation Libraries Not Found
+## ModelSim Simulation Libraries Not Found
 
 If running the setupenv.sh script returns an error like the following:
 

host/docs/fpga/usrp3/sim/simulation_libraries.md

@@ -1,4 +1,4 @@
-# Simulation Libraries
+\page usrp3_sim_simulation_libraries Simulation Libraries
 
 Several simulation libraries are available for use in your testbenches, in the
 form of SystemVerilog packages, classes, and interfaces. The bus functional
@@ -9,9 +9,9 @@ member functions and tasks for communicating with the BFMs.
 A few commonly used SystemVerilog packages are described below. See each
 package file for additional documentation.
 
-## PktTestExec
+# PkgTestExec
 
-`PktTestExec.sv` contains utilities for testbench reporting, assertions, and
+`PkgTestExec.sv` contains utilities for testbench reporting, assertions, and
 simulation timeouts. The associated header file, `test_exec.svh`, contains
 macros for use with PkgTestExec. These macros are used to implement
 SystemVerilog assertions. The header also defines `timeunit` and
@@ -20,7 +20,7 @@ SystemVerilog assertions. The header also defines `timeunit` and
 **Note:** The `timeunit` must be `1ns` in order for PkgTestExec to use
 and report times correctly.
 
-### PkgTestExec Tasks and Functions
+## PkgTestExec Tasks and Functions
 
 Below are some of the methods available in PkgTestExec. See `PkgTestExec.sv`
 for additional documentation.
@@ -52,7 +52,7 @@ manner and to report which timeout was exceeded.
 - <b>`end_timeout(timeout_t handle)`</b><br>
 Called to end a timeout countdown when it is no longer needed.
 
-### Macros
+## Macros
 
 The following macros are defined in `test_exec.svh`. These update internal
 variables to track the state of the testbench and to report the final results.
@@ -70,13 +70,13 @@ Where:
 - <b>`EXPR`</b> is the condition for the assertion (what you expect to be true)
 - <b>`MESSAGE`</b> is the message string to report if the assertion fails
 
-## PkgChdrUtils
+# PkgChdrUtils
 
 The `PkgChdrUtils` package includes various definitions and functions for
 interacting with the RFNoC network protocol, called the Condensed Hierarchical
 Datagram for RFNoC (CHDR). See `PkgChdrUtils.sv` for additional documentation.
 
-## PkgChdrData
+# PkgChdrData
 
 The `PkgChdrData` package contains the CHDR and item data types, as well as
 utilities, that are useful for interacting with RFNoC data. An *item* refers to
@@ -110,12 +110,12 @@ widths using the following example:
     // Convert the bytes to a queue of samples
     bytes = ChdrData#(ITEM_W, 8)::item_to_chdr(samples);
 
-## PkgRfnocBlockCtrlBfm
+# PkgRfnocBlockCtrlBfm
 
 The `PkgRfnocBlockCtrlBfm` package contains the `RfnocBlockCtrlBfm` bus
 functional model (BFM) used to emulate a software block controller for an RFNoC
 block. This is the BFM used to interact with an RFNoC block in simulation. See
-the \ref md_usrp3_sim_writing_sim_top "testbench example" for an example
+the \ref usrp3_sim_writing_sim_top "testbench example" for an example
 of how to instantiate and connect the BFM to your DUT.
 
 To be used, the BFM must be connected to the RFNoC block using an
@@ -153,7 +153,7 @@ underflow and overflow tolerance in your testbenches.
 Low-level tasks and functions are also available for inputting raw packets
 directly.
 
-## sim_clock_gen
+# sim_clock_gen
 
 The `sim_clock_gen` module makes it easy create clocks and synchronous resets,
 and to interact with them. See `sim_clock_gen.sv` for additional documentation.
@@ -166,7 +166,7 @@ Some features include:
 - Kill the clock (prevent any new simulation events)
 - Wait for \em n rising/falling clock edges
 
-## PkgAxiStream
+# PkgAxiStream
 
 The `PkgAxiStreamBfm` package contains the `AxistreamPacket` and `AxiStreamBfm`
 classes which are used to model AXI4-Stream interfaces in the testbenches.

host/docs/fpga/usrp3/sim/writing_sim_makefile.md

@@ -1,4 +1,4 @@
-# Writing a Simulation Makefile
+\page usrp3_sim_writing_sim_makefile Writing a Simulation Makefile
 
 The testbench Makefile tells the build tools what to build, where to build it,
 dependency information, and runtime information. The build infrastructure will
@@ -93,7 +93,7 @@ template for your RFNoC block.
 
 You will notice that the Makefile has 5 distinct sections.
 
-## Section 1: Boilerplate
+# Section 1: Boilerplate
 
     #-------------------------------------------------
     # Top-of-Makefile
@@ -119,7 +119,7 @@ This example uses the make variable UHD_FPGA_DIR to specify the location of the
 FPGA repository. This is useful for out-of-tree modules. UHD_FPGA_DIR is the
 variable used by CMake for the RFNoC examples.
 
-## Section 2: Design Specific
+# Section 2: Design Specific
 
     #-------------------------------------------------
     # Design Specific
@@ -159,7 +159,7 @@ The following makefile variables are special and should be defined:
 If `ARCH` and `PART_ID` are not specified, a default part will be assumed. This
 may be fine if your DUT doesn't have any architecture-specific IP.
 
-## Section 3: IP Specific
+# Section 3: IP Specific
 
     #-------------------------------------------------
     # IP Specific
@@ -194,7 +194,7 @@ IP sources.
 The IP included in this example may not be needed for your testbench, in which
 case it can be removed to reduce compile times.
 
-## Section 4: Testbench Specific
+# Section 4: Testbench Specific
 
     #-------------------------------------------------
     # Testbench Specific
@@ -222,7 +222,7 @@ The following variables should be defined:
 - `SIM_SRCS`: This is similar to DESIGN_SRCS except that it should contain a
   path to `SIM_TOP` and all of its dependencies.
 
-## Section 5: Tool Support
+# Section 5: Tool Support
 
     #-------------------------------------------------
     # Bottom-of-Makefile

host/docs/fpga/usrp3/sim/writing_sim_top.md

@@ -1,4 +1,4 @@
-# Writing a Top-level Simulation Module
+\page usrp3_sim_writing_sim_top Writing a Top-level Simulation Module
 
 The top-level simulation module will instantiate the DUT and implement
 self-checking behavior. Testbenches can be written in any language
@@ -9,7 +9,7 @@ An example testbench is shown below. This example is for an RFNoC block. If
 creating a testbench for RFNoC, it is recommended to use the RFNoC ModTool to
 generate a testbench template for your RFNoC block.
 
-See \ref md_usrp3_sim_simulation_libraries for documentation on the simulation
+See \ref usrp3_sim_simulation_libraries for documentation on the simulation
 libraries used in this example.
 
     //

host/docs/fpga/usrp3/sim/writing_testbenches.md

@@ -1,4 +1,4 @@
-# Writing a Testbench
+\page usrp3_sim_writing_testbenches Writing a Testbench
 
 Writing a unit test or system level test is easy with the Vivado makefile infrastructure! 
 Most of the overhead of building and running a testbench is handled by the build tools. 
@@ -6,8 +6,8 @@ Even recurring tasks like reporting and monitoring are implemented by framework
 
 Each executable FPGA unit test must have the following components:
 
-1. \ref md_usrp3_sim_writing_sim_makefile "A simulation Makefile"
-2. \ref md_usrp3_sim_writing_sim_top "A top-level simulation module"
+1. \subpage usrp3_sim_writing_sim_makefile "Writing A Simulation Makefile"
+2. \subpage usrp3_sim_writing_sim_top "Writing a Top-Level Simulation Module"
 
 If creating a testbench for an RFNoC block, it is recommended to use the RFNoC
 ModTool (rfnoc_create_verilog.py) to create a template Makefile and testbench
@@ -20,5 +20,4 @@ ease-of-use with particular protocols and subsystems.
 See the following manual pages for information about how to create the Makefile
 and top-level simulation file.
 
-- \subpage md_usrp3_sim_writing_sim_makefile "Writing a Simulation Makefile"
-- \subpage md_usrp3_sim_writing_sim_top "Writing a Top-level Simulation Module"
+See the manual pages linked above for information about how to create the Makefile and top-level simulation file.

host/docs/fpga/usrp3/simulation.md

@@ -0,0 +1,16 @@
+\page gen3_fpga_sim Simulation
+
+__Instructions__
+
+ - \subpage usrp3_sim_running_testbenches "Running a Testbench"
+ - \subpage usrp3_sim_writing_testbenches "Writing a Testbench"
+
+__Library Reference__
+
+ - \subpage usrp3_sim_simulation_libraries "Testbench Simulation Libraries"
+
+__Legacy Library Reference__
+
+ - \subpage usrp3_sim_legacy_testbenches "Legacy Testbenches"
+ - \subpage usrp3_sim_libs_general "Legacy General Purpose Simulation Libraries"
+ - \subpage usrp3_sim_libs_axi "Legacy AXI Interface Libraries"

host/docs/fpga/usrp3/usrp3_build_sim_instructions.md

@@ -0,0 +1,5 @@
+\page gen3_fpga_build_sim Generation 3 USRP Build Documentation
+
+\li \subpage gen3_fpga_build "Build Documentation"
+\li \subpage gen3_vivado_env_utils "Vivado Environment Utilities"
+\li \subpage gen3_fpga_sim "Simulation"

host/docs/fpga/usrp3/vivado_env_utils.md

@@ -1,6 +1,6 @@
-# Vivado Environment Utilities
+\page gen3_vivado_env_utils Vivado Environment Utilities
 
-## Environment Setup
+# Environment Setup
 
 - Navigate to `<repo>/fpga/usrp3/top/{project}` where {project} is:
   + `x300:` For USRP X300/X310
@@ -16,7 +16,7 @@
 - This should not only enable building USRP FPGAs but also make available the
   utilities described in the following sections.
 
-## ModelSim Specific
+# ModelSim Specific
 
 The `setupenv.sh` script will search the system for ModelSim installations and setup everything to run it natively and
 within Vivado. The currently supported versions of ModelSim are PE, DE, SE, DE-64, SE-64.
@@ -25,9 +25,9 @@ The following functions are also available in the environment:
 
     build_simlibs: Build ModelSim simulation libraries for Vivado
 
-## IP Management
+# IP Management
 
-### Create Vivado IP
+## Create Vivado IP
 
     viv_create_ip: Create a new Vivado IP instance and a Makefile for it
 
@@ -37,14 +37,14 @@ The following functions are also available in the environment:
     - <IP VLNV>: The vendor, library, name, and version (VLNV) string for the IP as defined by Xilinx
     - <Product>: Product to generate IP for
 
-### Modify existing Vivado IP
+## Modify existing Vivado IP
 
     viv_modify_ip: Modify an existing Vivado IP instance
 
     Usage: viv_modify_ip <IP XCI Path>
     - <IP XCI Path>: Path to the IP XCI file
 
-### Modify existing Vivado Block Design (BD)
+## Modify existing Vivado Block Design (BD)
 
     viv_modify_bd: Modify an existing Vivado BD instance
 
@@ -52,7 +52,7 @@ The following functions are also available in the environment:
     - <BD File Path>: Path to the BD file.
     - <Product>: Product to generate IP for
 
-### Modify existing Vivado Tcl-based Block Design
+## Modify existing Vivado Tcl-based Block Design
 
     viv_modify_tcl_bd: Modify an existing Vivado BD instance
 
@@ -60,35 +60,35 @@ The following functions are also available in the environment:
     - <Tcl File Path>: Path to the Tcl file for the block design.
     - <Product>: Product to generate IP for
 
-### List supported Vivado IP
+## List supported Vivado IP
 
     viv_ls_ip: List the items in the Vivado IP catalog
 
     Usage: viv_ls_ip <Product>
     - <Product>: Product to generate IP for.
 
-### Upgrade IP to the environment version of Vivado
+## Upgrade IP to the environment version of Vivado
 
     viv_upgrade_ip: Upgrade one or more Xilinx IP targets
 
     Usage: viv_upgrade_ip <IP Directory> [--recursive]
     - <IP Directory>: Path to the IP XCI file.
 
-## Hardware Management
+# Hardware Management
 
-### Launch Vivado Hardware Console
+## Launch Vivado Hardware Console
 
     viv_hw_console: Launch the Tcl hardware console
 
     Usage: viv_hw_console
 
-### List connected JTAG devices
+## List connected JTAG devices
 
     viv_jtag_list: List all devices (and their addresses) that are connected to the system using the Xilinx platform cable
 
     Usage: viv_jtag_list
 
-### Program device over JTAG
+## Program device over JTAG
 
     viv_jtag_program: Downloads a bitfile to an FPGA device using Vivado
 
@@ -97,9 +97,9 @@ The following functions are also available in the environment:
     - <Device Address>: Address to the device in the form <Target>:<Device>
                         Run viv_jtag_list to get a list of connected devices
 
-### Probe Xilinx bitfile
+## Probe Xilinx bitfile
 
-    probe_bitfile: Probe a Xilinx bitfile and report header information
+    probe_bitfile: Read a Xilinx bitfile and report the header information
 
     Usage: probe_bitfile <Bitfile Path>
     - <Bitfile Path>: Path to a .bit FPGA configuration file