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fpga: Upgrade to Vivado 2025.2: Repair all FPGA compiles
This commit is contained in:
Max Köhler
Max Köhler
parent
f3d6cd6c01
commit
0df07dcde8
@ -65,7 +65,7 @@ module axi_packet_gate #(
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ram_2port #(
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.DWIDTH (WIDTH+1), .AWIDTH(SIZE),
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.RW_MODE("NO-CHANGE"), .OUT_REG(0),
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.RAM_TYPE(SIZE <= LUTRAM_THRESH ? "LUTRAM" : "AUTOMATIC")
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.RAM_TYPE(SIZE <= LUTRAM_THRESH ? "LUTRAM" : "BRAM")
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) ram_i (
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.clka (clk), .ena(1'b1), .wea(wr_en),
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.addra(wr_addr), .dia(wr_data), .doa(),
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@ -504,7 +504,7 @@ module x4xx_qsfp_wrapper #(
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axi_hp_dma[lane].bready = 1'b0;
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axi_hp_dma[lane].rready = 1'b0;
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mgt_pause_req = 0'b0;
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mgt_pause_req = 1'b0;
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eth_rx_irq[lane] = 1'b0;
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eth_tx_irq[lane] = 1'b0;
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@ -133,7 +133,7 @@ module eth_ipv4_chdr_adapter_wrapper #(
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// Interface
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//---------------------------------------------------------------------------
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AxiStreamIf #(.DATA_WIDTH(ENET_W), .USER_WIDTH(ENET_USER_W), .TKEEP(0))
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AxiStreamIf #(.DATA_WIDTH(ENET_W), .USER_WIDTH(ENET_USER_W), .TKEEP(1))
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eth_tx (eth_clk, eth_rst);
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AxiStreamIf #(.DATA_WIDTH(ENET_W), .USER_WIDTH(ENET_USER_W), .TKEEP(0))
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eth_rx (eth_clk, eth_rst);
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@ -292,7 +292,7 @@ module eth_ipv4_internal #(
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localparam CPU_USER_W = $clog2(CPU_W/8)+1; // SOF + trailing bytes
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// Host DMA interfaces
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AxiStreamIf #(.DATA_WIDTH(CPU_W), .USER_WIDTH(CPU_USER_W), .TUSER(1), .TKEEP(0))
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AxiStreamIf #(.DATA_WIDTH(CPU_W), .USER_WIDTH(CPU_USER_W), .TUSER(1), .TKEEP(1))
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e2h_chdr(bus_clk, bus_rst);
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AxiStreamIf #(.DATA_WIDTH(CPU_W), .USER_WIDTH(CPU_USER_W), .TUSER(1), .TKEEP(0))
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h2e_chdr(bus_clk, bus_rst);
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@ -28,7 +28,7 @@ dict set e3xx_strategy "post_place_phys_opt_design.directive" "Default"
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dict set e3xx_strategy "route_design.directive" "Default"
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dict set e3xx_strategy "route_design.more_options" "-tns_cleanup"
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dict set e3xx_strategy "post_route_phys_opt_design.is_enabled" 1
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dict set e3xx_strategy "post_route_phys_opt_design.directive" "Default"
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dict set e3xx_strategy "post_route_phys_opt_design.directive" "ExploreWithAggressiveHoldFix"
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vivado_strategies::implement_design $e3xx_strategy
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# STEP#4: Generate reports
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@ -21,14 +21,14 @@ dict set n3xx_strategy "implementation.incremental" 0
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dict set n3xx_strategy "opt_design.is_enabled" 1
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dict set n3xx_strategy "opt_design.directive" "NoBramPowerOpt"
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dict set n3xx_strategy "post_opt_power_opt_design.is_enabled" 0
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dict set n3xx_strategy "place_design.directive" "ExtraNetDelay_high"
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dict set n3xx_strategy "place_design.directive" "Explore"
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dict set n3xx_strategy "post_place_power_opt_design.is_enabled" 0
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dict set n3xx_strategy "post_place_phys_opt_design.is_enabled" 1
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dict set n3xx_strategy "post_place_phys_opt_design.directive" "AggressiveExplore"
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dict set n3xx_strategy "route_design.directive" "Explore"
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dict set n3xx_strategy "route_design.more_options" "-tns_cleanup"
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dict set n3xx_strategy "post_route_phys_opt_design.is_enabled" 1
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dict set n3xx_strategy "post_route_phys_opt_design.directive" "Explore"
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dict set n3xx_strategy "post_route_phys_opt_design.directive" "ExploreWithAggressiveHoldFix"
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vivado_strategies::implement_design $n3xx_strategy
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# STEP#4: Generate reports
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@ -16,6 +16,8 @@ module ten_gige_phy_clk_gen
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wire clk156_buf;
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wire dclk_buf;
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wire clkfbout;
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wire clkfb;
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wire refclk_buf;
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IBUFDS_GTE2 ibufds_inst (
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.O (refclk),
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@ -25,21 +27,50 @@ module ten_gige_phy_clk_gen
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.IB (refclk_n)
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);
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BUFG clk156_bufg_inst (
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// required buffer to get differential refclock from clock region without PLL instance to another
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// one
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BUFG refclk_bufg_inst (
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.I (refclk),
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.O (refclk_buf)
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);
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// Clock cleanup required with Vivado 2025.2 to remove hold timing violations downstream
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PLLE2_BASE #(
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.BANDWIDTH("HIGH"),
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.CLKFBOUT_MULT(10),
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(6.4),
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.CLKOUT0_DIVIDE(10),
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.CLKOUT1_DIVIDE(20),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER1(0.010),
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.STARTUP_WAIT("FALSE")
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) pll_clk156_inst (
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.CLKOUT0(clk156_buf),
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.CLKOUT1(dclk_buf),
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.CLKOUT2(),
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.CLKOUT3(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKFBOUT(clkfbout),
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.LOCKED(),
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.CLKIN1(refclk_buf),
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.PWRDWN(1'b0),
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.RST(areset),
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.CLKFBIN(clkfb)
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);
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// PLL feedback clock buffer
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BUFG clkfb_bufg_inst (
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.I (clkfbout),
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.O (clkfb)
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);
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// buffer for generated clocks
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BUFG clk156_bufg_inst (
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.I (clk156_buf),
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.O (clk156)
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);
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// Divding independent clock by 2 as source for DRP clock
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BUFR # (
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.BUFR_DIVIDE ("2")
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) dclk_divide_by_2_buf (
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.I (clk156),
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.O (dclk_buf),
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.CE (1'b1),
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.CLR (1'b0)
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);
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BUFG dclk_bufg_i (
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.I (dclk_buf),
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.O (dclk)
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@ -10,10 +10,10 @@ set_property PACKAGE_PIN R7 [get_ports XG_CLK_n]
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create_clock -name XG_CLK -period 6.400 -waveform {0.000 3.200} [get_ports XG_CLK_p]
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set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks XG_CLK]
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set_clock_groups -asynchronous -group [get_clocks bus_clk_div2] -group [get_clocks XG_CLK]
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set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}] -group [get_clocks XG_CLK]
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set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}] -group [get_clocks XG_CLK]
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set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks XG_CLK -include_generated_clocks]
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set_clock_groups -asynchronous -group [get_clocks bus_clk_div2] -group [get_clocks XG_CLK -include_generated_clocks]
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set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}] -group [get_clocks XG_CLK -include_generated_clocks]
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set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}] -group [get_clocks XG_CLK -include_generated_clocks]
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set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *PRE}]
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set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *CLR}]
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@ -145,7 +145,7 @@ X420_IP: ##Build X420 IP only. Use the -j option to build multiple IP block
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+$(call vivado_ip,X420,$(DEFS) X420=1)
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X440_IP: ##Build X440 IP only. Use the -j option to build multiple IP blocks simultaneously.
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+$(call vivado_ip,X440,$(DEFS) X440=1)
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+$(call vivado_ip,X440,$(DEFS) X440=1) BUILD_ALL_X440_RFDC=1
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$(BUILD_DIR)/x410-version-info.dtsi: regmap/x410/versioning_regs_regmap_utils.vh
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tools/parse_versions_for_dts.py \
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@ -20,9 +20,6 @@ BASE_DIR = $(abspath ..)
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IP_DIR = $(abspath ./ip)
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include $(BASE_DIR)/../tools/make/viv_design_builder.mak
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# Include IP directory
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include $(IP_DIR)/Makefile.inc
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# Include any LIB dependencies
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include coregen_dsp/Makefile.srcs
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include $(LIB_DIR)/control/Makefile.srcs
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@ -51,6 +48,9 @@ ifdef BUILD_DIR
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include $(BUILD_DIR)/Makefile.inc
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endif
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# Include IP directory
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include $(IP_DIR)/Makefile.inc
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##################################################
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# Sources
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##################################################
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@ -10,10 +10,6 @@ source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl
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# STEP#1: Create project, add sources, refresh IP
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vivado_utils::initialize_project
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# STEP#1.5: Modify block diagram if needed
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set script_dir [file dirname [info script]]
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source [file join $script_dir x4xx_bd_modification.tcl]
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# STEP#2: Run synthesis
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vivado_utils::synthesize_design
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vivado_utils::generate_post_synth_reports
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@ -23,12 +19,8 @@ vivado_utils::exit_if_synth_only
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set strategy [vivado_strategies::get_impl_preset "Performance_ExplorePostRoutePhysOpt"]
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# Enable incremental build
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dict set strategy "implementation.incremental" $::env(VIV_INCR_BUILD)
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# Turn up uncertainty on 100Gb clocks(-quiet so if it fails because the clocks don't exist, it won't error)
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set_clock_uncertainty 0.5 -quiet -setup [get_clocks txoutclk_out*]
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# Vivado has been underestimating routing delays.
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dict set strategy "place_design.directive" "ExtraNetDelay_high"
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# Turn down uncertainty on 100Gb clocks
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dict set strategy "route_design.pre_hook" {set_clock_uncertainty 0.0 -quiet -setup [get_clocks txoutclk_out*]}
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vivado_strategies::implement_design $strategy
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# STEP#4: Generate reports
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@ -43,12 +43,12 @@ include $(IP_DIR)/adc_100m_bd/Makefile.inc
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include $(IP_DIR)/dac_100m_bd/Makefile.inc
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include $(IP_DIR)/ddr4_64bits_x440/Makefile.inc
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include $(IP_DIR)/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/Makefile.inc
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include $(IP_DIR)/x4xx_ps_rfdc_bd/x440_2spc_ps_rfdc_bd/Makefile.inc
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include $(IP_DIR)/fir_dec3_2spc/Makefile.inc
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include $(IP_DIR)/fir_inp3_1spc/Makefile.inc
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endif
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BD_SRCS = \
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$(IP_X4XX_PS_RFDC_BD_SRCS) \
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$(IP_X4XX_PS_RFDC_HDL_SRCS) \
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$(IP_AXI_INTERCONNECT_APP_BD_SRCS) \
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$(IP_AXI_INTERCONNECT_ETH_BD_SRCS) \
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@ -81,11 +81,25 @@ $(IP_DAC_400M_HDL_SRCS)
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endif
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ifdef X440
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# Both X440 RFDC block-diagram Makefiles assign the same source and output
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# variables. For a binary target, select only the RFDC variant required by
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# the image core so the shared variables identify the correct sources. For
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# the IP target, BUILD_ALL_X440_RFDC selects both variants so all generated
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# IP is available.
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ifeq ($(BUILD_ALL_X440_RFDC),1)
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BD_SRCS += $(IP_X4XX_PS_RFDC_BD_SRCS) $(IP_X4XX_2SPC_PS_RFDC_BD_SRCS)
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else ifneq (,$(findstring X440_2SPC_PS_RFDC_BD=1,$(RFNOC_IMAGE_CORE_DEFS)))
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BD_SRCS += $(IP_X4XX_2SPC_PS_RFDC_BD_SRCS)
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else
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BD_SRCS += $(IP_X4XX_PS_RFDC_BD_SRCS)
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endif
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BD_SRCS += \
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$(IP_ADC_100M_BD_SRCS) \
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$(IP_ADC_100M_HDL_SRCS) \
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$(IP_DAC_100M_BD_SRCS) \
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$(IP_DAC_100M_HDL_SRCS)
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else # default case for non-X440 devices
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BD_SRCS += $(IP_X4XX_PS_RFDC_BD_SRCS)
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endif
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IP_XCI_SRCS = \
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@ -114,7 +128,6 @@ $(IP_FIR_INP3_1SPC_SRCS)
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endif
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BD_OUTPUTS = \
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$(BD_X4XX_PS_RFDC_BD_OUTS) \
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$(BD_AXI_INTERCONNECT_APP_BD_OUTS) \
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$(BD_AXI_INTERCONNECT_ETH_BD_OUTS) \
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$(BD_AXI_INTERCONNECT_DMA_BD_OUTS) \
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@ -129,6 +142,15 @@ $(BD_AXI_INTER_2X512_512_BD_OUTS) \
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$(BD_100G_BD_OUTS) \
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$(BD_AXI_ETH_DMA_BD_OUTS)
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# See the X440 BD_SRCS selection above for why these RFDC outputs are selected.
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ifeq ($(BUILD_ALL_X440_RFDC),1)
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BD_OUTPUTS += $(BD_X4XX_PS_RFDC_BD_OUTS) $(BD_X4XX_2SPC_PS_RFDC_BD_OUTS)
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else ifneq (,$(findstring X440_2SPC_PS_RFDC_BD=1,$(RFNOC_IMAGE_CORE_DEFS)))
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BD_OUTPUTS += $(BD_X4XX_2SPC_PS_RFDC_BD_OUTS)
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else
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BD_OUTPUTS += $(BD_X4XX_PS_RFDC_BD_OUTS)
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endif
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ifdef X410
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BD_OUTPUTS += \
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$(BD_ADC_100M_BD_OUTS) \
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@ -0,0 +1,37 @@
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#
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# Copyright 2026 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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IP_X4XX_2SPC_PS_RFDC_ORIG_SRCS = \
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$(IP_BUILD_DIR)/x440_2spc_ps_rfdc_bd_base/x440_2spc_ps_rfdc_bd_base.tcl \
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$(IP_DIR)/x4xx_ps_rfdc_bd/x440_2spc_ps_rfdc_bd/x440_2spc_ps_rfdc_bd.tcl
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IP_X4XX_2SPC_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x440_2spc_ps_rfdc_bd/, \
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x440_2spc_ps_rfdc_bd.tcl \
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)
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IP_X4XX_2SPC_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x440_2spc_ps_rfdc_bd/, \
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x440_2spc_ps_rfdc_bd/x440_2spc_ps_rfdc_bd.bd \
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)
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BD_X4XX_2SPC_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x440_2spc_ps_rfdc_bd/, \
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x440_2spc_ps_rfdc_bd.bd.out \
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x440_2spc_ps_rfdc_bd/x440_2spc_ps_rfdc_bd_ooc.xdc \
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x440_2spc_ps_rfdc_bd/synth/x440_2spc_ps_rfdc_bd.v \
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)
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.INTERMEDIATE: IP_X4XX_2SPC_PS_RFDC_BD_TRGT
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$(IP_X4XX_2SPC_PS_RFDC_BD_SRCS) $(BD_X4XX_2SPC_PS_RFDC_BD_OUTS) $(IP_X4XX_2SPC_PS_RFDC_BDTCL_SRCS): IP_X4XX_2SPC_PS_RFDC_BD_TRGT
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@:
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IP_X4XX_2SPC_PS_RFDC_BD_TRGT: $(IP_X4XX_2SPC_PS_RFDC_ORIG_SRCS)
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$(call BUILD_VIVADO_BDTCL,x440_2spc_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR)/x4xx_ps_rfdc_bd,$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS))
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# derive the base diagram by adding "2spc" to all strings
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# This ensures that generated clock domain naming like "x440_2spc_ps_rfdc_bd_pll_ref_clk_in" still
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# works fine after renaming.
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$(IP_BUILD_DIR)/x440_2spc_ps_rfdc_bd_base/x440_2spc_ps_rfdc_bd_base.tcl: $(IP_DIR)/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/x440_ps_rfdc_bd.tcl
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mkdir -p $(dir $@)
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sed 's/x440_ps_rfdc_bd/x440_2spc_ps_rfdc_bd/g' $< > $@
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@ -0,0 +1,76 @@
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#
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# Copyright 2026 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Module: x440_2spc_ps_rfdc_bd
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#
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# Description:
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#
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# Manual X440 RFDC block-design wrapper for the 2-samples-per-cycle
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# configuration. The base block-design Tcl is generated from the original
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# X440 design with its design and clock-domain names adapted for this
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# variant. This script applies the RFDC data-width and interface-width
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# changes required by the 2-SPC datapath, then validates and saves the
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# resulting block design.
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#
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# Reuse the original x440 block diagram after renaming.
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source ../x440_2spc_ps_rfdc_bd_base/x440_2spc_ps_rfdc_bd_base.tcl
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# Change the RFDC data path to 2 samples / cycle.
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# This requires the decimation and interpolation modes to be set to 8.
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# As the original configuration is 8 samples / cycle at using 2 times
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# resampling the clock rates stay the same.
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set_property -dict [list \
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CONFIG.ADC0_Multi_Tile_Sync {true} \
|
||||
CONFIG.ADC_Decimation_Mode00 {8} \
|
||||
CONFIG.ADC_Data_Width00 {2} \
|
||||
CONFIG.ADC_Decimation_Mode01 {8} \
|
||||
CONFIG.ADC_Data_Width01 {2} \
|
||||
CONFIG.ADC_Data_Width02 {2} \
|
||||
CONFIG.ADC_Data_Width03 {2} \
|
||||
CONFIG.ADC1_Multi_Tile_Sync {true} \
|
||||
CONFIG.ADC_Data_Width10 {2} \
|
||||
CONFIG.ADC_Data_Width11 {2} \
|
||||
CONFIG.ADC_Data_Width12 {2} \
|
||||
CONFIG.ADC_Data_Width13 {2} \
|
||||
CONFIG.ADC2_Multi_Tile_Sync {true} \
|
||||
CONFIG.ADC_Data_Width20 {2} \
|
||||
CONFIG.ADC_Data_Width21 {2} \
|
||||
CONFIG.ADC_Data_Width22 {2} \
|
||||
CONFIG.ADC_Data_Width23 {2} \
|
||||
CONFIG.ADC3_Multi_Tile_Sync {true} \
|
||||
CONFIG.ADC_Data_Width30 {2} \
|
||||
CONFIG.ADC_Data_Width31 {2} \
|
||||
CONFIG.ADC_Data_Width32 {2} \
|
||||
CONFIG.ADC_Data_Width33 {2} \
|
||||
CONFIG.DAC0_Multi_Tile_Sync {true} \
|
||||
CONFIG.DAC_Data_Width00 {4} \
|
||||
CONFIG.DAC_Data_Width01 {4} \
|
||||
CONFIG.DAC_Data_Width02 {4} \
|
||||
CONFIG.DAC_Data_Width03 {4} \
|
||||
CONFIG.DAC1_Multi_Tile_Sync {true} \
|
||||
CONFIG.DAC_Data_Width10 {4} \
|
||||
CONFIG.DAC_Data_Width11 {4} \
|
||||
CONFIG.DAC_Data_Width12 {4} \
|
||||
CONFIG.DAC_Data_Width13 {4} \
|
||||
] [get_bd_cells rfdc/rf_data_converter]
|
||||
|
||||
|
||||
# The changed RFDC interfaces have to be reflected in the upstream AXI
|
||||
# interfaces. A change to 2 samples/cycle is required for the calibration
|
||||
# muxes.
|
||||
set_property -dict [list CONFIG.kAxiWidth {64}] [get_bd_cells rfdc/calibration_muxes/gpio_to_axis_mux_0]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile228_ch0_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile228_ch1_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile228_ch2_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile228_ch3_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile229_ch0_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile229_ch1_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile229_ch2_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile229_ch3_din]
|
||||
|
||||
# revalidate and save the block design
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
@ -1886,7 +1886,11 @@ module x4xx (
|
||||
.clk_adc0 ()
|
||||
);
|
||||
`elsif X440
|
||||
`ifdef X440_2SPC_PS_RFDC_BD
|
||||
x440_2spc_ps_rfdc_bd x440_ps_rfdc_bd_i (
|
||||
`else
|
||||
x440_ps_rfdc_bd x440_ps_rfdc_bd_i (
|
||||
`endif
|
||||
.adc_enable_data_r0clk (adc_enable_data_rclk[0]),
|
||||
.adc_enable_data_r1clk (adc_enable_data_rclk[1]),
|
||||
.adc_reset_pulse_r0clk (adc_reset_pulse[0]),
|
||||
|
||||
@ -1,83 +0,0 @@
|
||||
|
||||
# Extract the Verilog defines from the environment (optional variable)
|
||||
set viv_defs ""
|
||||
if { [info exists ::env(VIV_VERILOG_DEFS)] } {
|
||||
set viv_defs $::env(VIV_VERILOG_DEFS)
|
||||
}
|
||||
|
||||
# Only apply these modifications for X440 with 200M RF bandwidth image
|
||||
if {[regexp {X440=1} $viv_defs] && [regexp {RF_BW=200} $viv_defs] && [regexp {USE_FABRIC_RESAMPLERS=1} $viv_defs]} {
|
||||
|
||||
# print a message to indicate that the modifications are being applied
|
||||
puts "Applying X440 200M RF modifications to block design"
|
||||
|
||||
# Load the custom HDL sources required by the block design IP before opening it.
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
source [file join $script_dir ip x4xx_ps_rfdc_bd x440_ps_rfdc_bd hdl_sources.tcl]
|
||||
|
||||
# open the existing block design
|
||||
open_bd_design [get_files x440_ps_rfdc_bd.bd]
|
||||
|
||||
# Change the RFDC data path to 2 samples / cycle.
|
||||
# This requires the decimation and interpolation modes to be set to 8.
|
||||
# As the original configuration is 8 samples / cycle at using 2 times
|
||||
# resampling the clock rates stay the same.
|
||||
set_property -dict [list \
|
||||
CONFIG.ADC0_Multi_Tile_Sync {true} \
|
||||
CONFIG.ADC_Decimation_Mode00 {8} \
|
||||
CONFIG.ADC_Data_Width00 {2} \
|
||||
CONFIG.ADC_Decimation_Mode01 {8} \
|
||||
CONFIG.ADC_Data_Width01 {2} \
|
||||
CONFIG.ADC_Data_Width02 {2} \
|
||||
CONFIG.ADC_Data_Width03 {2} \
|
||||
CONFIG.ADC1_Multi_Tile_Sync {true} \
|
||||
CONFIG.ADC_Data_Width10 {2} \
|
||||
CONFIG.ADC_Data_Width11 {2} \
|
||||
CONFIG.ADC_Data_Width12 {2} \
|
||||
CONFIG.ADC_Data_Width13 {2} \
|
||||
CONFIG.ADC2_Multi_Tile_Sync {true} \
|
||||
CONFIG.ADC_Data_Width20 {2} \
|
||||
CONFIG.ADC_Data_Width21 {2} \
|
||||
CONFIG.ADC_Data_Width22 {2} \
|
||||
CONFIG.ADC_Data_Width23 {2} \
|
||||
CONFIG.ADC3_Multi_Tile_Sync {true} \
|
||||
CONFIG.ADC_Data_Width30 {2} \
|
||||
CONFIG.ADC_Data_Width31 {2} \
|
||||
CONFIG.ADC_Data_Width32 {2} \
|
||||
CONFIG.ADC_Data_Width33 {2} \
|
||||
CONFIG.DAC0_Multi_Tile_Sync {true} \
|
||||
CONFIG.DAC_Data_Width00 {4} \
|
||||
CONFIG.DAC_Data_Width01 {4} \
|
||||
CONFIG.DAC_Data_Width02 {4} \
|
||||
CONFIG.DAC_Data_Width03 {4} \
|
||||
CONFIG.DAC1_Multi_Tile_Sync {true} \
|
||||
CONFIG.DAC_Data_Width10 {4} \
|
||||
CONFIG.DAC_Data_Width11 {4} \
|
||||
CONFIG.DAC_Data_Width12 {4} \
|
||||
CONFIG.DAC_Data_Width13 {4} \
|
||||
] [get_bd_cells rfdc/rf_data_converter]
|
||||
|
||||
|
||||
# The changed RFDC interfaces have to be reflected in the upstream AXI
|
||||
# interfaces. A change to 2 samples/cycle is required for the calibration
|
||||
# muxes.
|
||||
set_property -dict [list CONFIG.kAxiWidth {64}] [get_bd_cells rfdc/calibration_muxes/gpio_to_axis_mux_0]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile228_ch0_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile228_ch1_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile228_ch2_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile228_ch3_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile229_ch0_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile229_ch1_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile229_ch2_din]
|
||||
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_intf_ports dac_tile229_ch3_din]
|
||||
|
||||
# revalidate and save the block design
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
|
||||
# regenerate the output products to avoid any stale intermediate files
|
||||
generate_target all [get_files x440_ps_rfdc_bd.bd]
|
||||
|
||||
# close the block design after applying all changes
|
||||
close_bd_design [current_bd_design]
|
||||
}
|
||||
@ -74,7 +74,7 @@ make_defs:
|
||||
- DRAM_BANKS=${0 if not parameters['ENABLE_DRAM'] else parameters['NUM_DRAM_BANKS']}
|
||||
- DRAM_CH=${0 if not parameters['ENABLE_DRAM'] else parameters['NUM_DRAM_CHANS']}
|
||||
- DRAM_W=${parameters['DRAM_WIDTH']}
|
||||
- USE_FABRIC_RESAMPLERS=${1 if parameters['USE_FABRIC_RESAMPLERS'] else 0}
|
||||
- ${"X440_2SPC_PS_RFDC_BD=1" if parameters['USE_FABRIC_RESAMPLERS'] else ""}
|
||||
- DISABLE_TX=${1 if parameters['DISABLE_TX'] else 0}
|
||||
- ENABLE_CLOCK_WD=${1 if parameters['ENABLE_CLOCK_WD'] else 0}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user