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ci: x420: Add devtests to pipeline
This makes the X420 devtests run in the test pipeline.
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@ -20,8 +20,9 @@ jobs:
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toolset: 'make'
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runPyTest: true
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runPyTestNonRF: false
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runDevTest: false
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runDevTest: true
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runSystemImageTest: false
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master_clock_rate: '245.76e6'
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uhdArtifactSource: ${{ parameters.uhdArtifactSource }}
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uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
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fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
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@ -31,7 +32,7 @@ jobs:
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dre_s156-x420-0:
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dutName: 'dre_s156-x420-0'
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dutType: 'x4xx'
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devtestPattern: 'x4x0'
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devtestPattern: 'x420'
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dutFPGA: 'CG_1000'
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dutEmbeddedImagesArtifact: 'x4xx-images'
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uartSerial: '2516353BE43C'
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@ -26,23 +26,30 @@ from rx_samples_to_file_test import RxSamplesToFileTest
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from tx_bursts_test import UhdTxBurstsTest
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from test_pps_test import UhdTestPpsTest
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from gpio_test import GpioTest
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GpioTest.tests = {}
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for port in ["GPIO0", "GPIO1"]:
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for bank, driver in [("GPIOA", "DB0_RF0")]:
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GpioTest.tests[f"{port}_{driver}"] = {
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"addl_args": [
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"--src",
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" ".join([driver] * 12),
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"--bank",
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bank,
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"--port",
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port,
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"--bits",
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"12",
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],
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}
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### The GPIO tests only work either with 100 Gbps NIC and 245.72 MHz master clock rate
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### or with the X4_200 FPGA image which has resamplers enabled. If one of these conditions
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### is not met, the GPIO tests will fail because streaming won't be stable and thus the
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### ATR states will flicker between the expected and the idle state. Therefore they are
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## disabled by default.
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# from gpio_test import GpioTest
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#
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# GpioTest.tests = {}
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# for port in ["GPIO0", "GPIO1"]:
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# for bank, driver in [("GPIOA", "DB0_RF0")]:
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# GpioTest.tests[f"{port}_{driver}"] = {
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# "addl_args": [
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# "--src",
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# " ".join([driver] * 12),
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# "--bank",
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# bank,
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# "--port",
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# port,
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# "--bits",
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# "12",
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# ],
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# }
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from gpio_test import GpioX4xxSetGetSourceTest
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