ci: x420: Add devtests to pipeline

This makes the X420 devtests run in the test pipeline.
This commit is contained in:
ahmedsalman-ni 2026-03-16 12:09:58 +01:00 committed by mkoop-ni
parent e836c84654
commit 09887343b0
2 changed files with 26 additions and 18 deletions

View File

@ -20,8 +20,9 @@ jobs:
toolset: 'make'
runPyTest: true
runPyTestNonRF: false
runDevTest: false
runDevTest: true
runSystemImageTest: false
master_clock_rate: '245.76e6'
uhdArtifactSource: ${{ parameters.uhdArtifactSource }}
uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
@ -31,7 +32,7 @@ jobs:
dre_s156-x420-0:
dutName: 'dre_s156-x420-0'
dutType: 'x4xx'
devtestPattern: 'x4x0'
devtestPattern: 'x420'
dutFPGA: 'CG_1000'
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '2516353BE43C'

View File

@ -26,23 +26,30 @@ from rx_samples_to_file_test import RxSamplesToFileTest
from tx_bursts_test import UhdTxBurstsTest
from test_pps_test import UhdTestPpsTest
from gpio_test import GpioTest
GpioTest.tests = {}
for port in ["GPIO0", "GPIO1"]:
for bank, driver in [("GPIOA", "DB0_RF0")]:
GpioTest.tests[f"{port}_{driver}"] = {
"addl_args": [
"--src",
" ".join([driver] * 12),
"--bank",
bank,
"--port",
port,
"--bits",
"12",
],
}
### The GPIO tests only work either with 100 Gbps NIC and 245.72 MHz master clock rate
### or with the X4_200 FPGA image which has resamplers enabled. If one of these conditions
### is not met, the GPIO tests will fail because streaming won't be stable and thus the
### ATR states will flicker between the expected and the idle state. Therefore they are
## disabled by default.
# from gpio_test import GpioTest
#
# GpioTest.tests = {}
# for port in ["GPIO0", "GPIO1"]:
# for bank, driver in [("GPIOA", "DB0_RF0")]:
# GpioTest.tests[f"{port}_{driver}"] = {
# "addl_args": [
# "--src",
# " ".join([driver] * 12),
# "--bank",
# bank,
# "--port",
# port,
# "--bits",
# "12",
# ],
# }
from gpio_test import GpioX4xxSetGetSourceTest