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fpga: lib: fixup simple_uart instantiation
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@ -183,7 +183,8 @@ module ctrlport_to_wb_uart #(
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.rx_int_o(),
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.tx_int_o(),
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.tx_o(uart_tx),
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.rx_i(uart_rx)
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.rx_i(uart_rx),
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.baud_o()
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);
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endmodule
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